Cong-Kha Pham’s research while affiliated with University of Electro-Communications and other places

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Publications (201)


A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator
  • Conference Paper

December 2024

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2 Reads

Tuan-Kiet Dang

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Trong- Thuc Hoang

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Cong-Kha Pham



Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC

December 2024

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19 Reads

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Side-channel analysis attacks have become the primary method for exploiting the vulnerabilities of cryptographic devices. Therefore, focusing on countermeasures to enhance the security level of these implementations evolves even more urgently. This article proposes a time-based hiding countermeasure by using spread-spectrum signals. In our RISC-V system on chip (SoC), cryptographic accelerators are given by random dynamic frequency-hopping signals. We found 223 available parameter sets for a Xilinx Mixed-Mode Clock Manage primitive in spread spectrum mode and achieved better effectiveness in the occupied bandwidth (OBW) metric. The mixed mode clock managers (MMCMs) output signal and the range of frequencies within the spread will be changed randomly, resulting in multiple clocks for individual encryption. The effectiveness of this proposal is demonstrated by conducting realistic side-channel attacks (SCAs) and state-of-the-art leakage assessment methodologies on the well-known data encryption standard, i.e., the Advanced Encryption Standard (AES) accelerator. Even though we used up to five million power traces, the test results show that our defense can stand up to a regular correlation power analysis (CPA) attack as well as alignment preprocessing methods, like CPA attacks that use a sliding window or an amplitude peak location algorithm. Furthermore, the t -test methodology cannot detect any first-order information leakage in five million traces; meanwhile, the deep learning leakage assessment (DLLA) requires nearly one million power traces in the training test to detect leakage points.







Efficient Hardware Implementation of the Lightweight CRYSTALS-Kyber

August 2024

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4 Reads

IEEE Transactions on Circuits and Systems I Regular Papers

Quantum computing raises questions about the security of data encrypted using modern methods. Hence, the National Institute of Standards and Technology (NIST) has undertaken standardization of post-quantum cryptography (PQC) algorithms to defend against attacks from both classical and quantum computers. Following four rounds of evaluation, CRYSTALS-Kyber has been selected for standardization. In this paper, we present an efficient hardware architecture of CRYSTALS-Kyber for resource-constrained IoT devices. Firstly, we propose a compact hash module for CRYSTALS-Kyber. A single buffer is designed to perform padding, hashing, and holding data. Hence, using large FIFOs for data input/output is eliminated. Then, we propose a novel non-memory-based iterative number theoretic transform (NMI-NTT) architecture. Finally, the data flow between modules is optimized to improve parallelization and execution time. Implementation results on an Artix-7 FPGA show that our design consumes minimal hardware resources compared to the designs reported to date, corresponding to 5487 LUTs, 3426 FFs, 1548 SLICEs, 3.5 BRAMs, and 2 DSPs. Our design computes key generation, encapsulation, and decapsulation phases in 3.3/4.5/6.1 K-cycles for Kyber512, 5.6/7.1/9.2 K-cycles for Kyber768, and 8.5/10.1/12.9 K-cycles for Kyber1024, with 185MHz operating frequency. Our area-time-product (ATP) performance outperforms other designs.


Citations (55)


... Performance comparisons with other lightweight ciphers, such as Grain128-AEAD, reveal that ASCON excels in encryption and decryption tasks while maintaining efficient, secure communication protocols [7], [9]. Additionally, ASCON's lightweight design addresses the growing demand for post-quantum cryptography (PQC), offering quantum-resistant security solutions that are essential in the face of emerging threats [8], [11]. Additional studies, such as [12], introduce lightweight interfaces to reduce implementation costs, albeit with certain design simplifications. ...

Reference:

Implementation and Performance of Lightweight Authentication Encryption ASCON on IoT Devices
ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications
  • Citing Article
  • January 2024

IEEE Transactions on Circuits and Systems II: Express Briefs

... By loading RT-Thread in the on-chip bootloader [8], physical isolation between RT-Thread and user applications can be effectively achieved, reducing program compile time and improving development efficiency. The key elements of deploying RT-Thread on processors with different architectures have been deeply analyzed, and the implementation of RT-Thread deployment on RISC-V architecture application processor D1-H has been successfully achieved [9]- [11]. For applications with strict real-time requirements, such as those requiring millisecond or even microsecond precision, real-time performance is a crucial factor to consider when choosing an RTOS. ...

RISC-V-Based System-on-Chips for IoT Applications
  • Citing Conference Paper
  • August 2024

... Nguyen et al. [25] presented a unified-pipelined NTT architecture employing the K-RED algorithm, LUTs, concatenation operations, and Vedic multipliers. This approach achieved a significant ATP reduction (53% to 94%) compared to existing designs when implemented on a Xilinx FPGA. ...

Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems
  • Citing Conference Paper
  • May 2024

... The centered EEG signal is then decomposed into multiple sub-bands using the MODWT. Unlike the discrete wavelet transform, MODWT preserves the signal's original length and temporal alignment by not downsampling [27]. This enables a more precise analysis of the signal's frequency components. ...

A Novel ECG Signal Quality Index Method based on Skewness-MODWT Analysis
  • Citing Article
  • Full-text available
  • May 2024

IEEE Access

... Among block cipher components, the S-box (Substitution box) is the most critical element, playing a vital role in providing nonlinearity to secure data against cryptographic attacks [4]. Consequently, optimizing S-box design is one of the primary challenges when implementing block ciphers on hardware [5]. ...

Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps

IEEE Access

... Several techniques have been adopted to mitigate the risks of cyber-attacks, such as authentication procedures to prevent unauthorized access to the system [11,12], cryptographic data obfuscation to make the information useless to malicious users listening to ...

Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications

Future Internet

... Infra-slow oscillations (<0.5 Hz), observed in preterm neonates and non-REM sleep [14]; • Delta waves (0.5-4 Hz), associated with deep sleep and found in infants and children [15]; • Theta waves (4-7 Hz), linked to drowsiness and early sleep stages (N1, N2) [15]; • Alpha waves (8)(9)(10)(11)(12), seen during quiet wakefulness, especially when eyes are closed [16]; • Beta waves (13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30), present during active concentration and task completion [16]; • Gamma waves , occurring in all brain states, prominent during alertness [17]; • High-frequency oscillations (>80 Hz), including ripples (80-250 Hz) and fast ripples (>250 Hz), related to memory encoding and cognitive process synchronization [18]. ...

Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process
  • Citing Article
  • December 2023

REV Journal on Electronics and Communications

... Avoided Technique(s) [13] ✓ --✓ Pipelining [23] ✓ --✓ Parallelism [17] ✓ --✓ Naive [16] ✓ -✓ -Merging NTT layers [24] -✓ -✓ Distributed memories [25] -✓ ✓ -Distributed memories [26] ✓ -✓ -Pipelining [27] ✓ -✓ -Pipelining [28] ✓ --✓ Pipelining [29] ✓ --✓ Radix-2/-4 butterfly [30] ✓ --✓ K 2 -RED [31] ✓ -✓ -Pipelining [32] ✓ --✓ Pipelining [33] ✓ -✓ -Parallel butterflies [34] ✓ -✓ Pipelining [35] ✓ - ...

High-speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium

IEEE Access

... Infra-slow oscillations (<0.5 Hz), observed in preterm neonates and non-REM sleep [14]; • Delta waves (0.5-4 Hz), associated with deep sleep and found in infants and children [15]; • Theta waves (4-7 Hz), linked to drowsiness and early sleep stages (N1, N2) [15]; • Alpha waves (8)(9)(10)(11)(12), seen during quiet wakefulness, especially when eyes are closed [16]; • Beta waves (13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30), present during active concentration and task completion [16]; • Gamma waves , occurring in all brain states, prominent during alertness [17]; • High-frequency oscillations (>80 Hz), including ripples (80-250 Hz) and fast ripples (>250 Hz), related to memory encoding and cognitive process synchronization [18]. ...

Design of a Configurable Low-Noise 1-Channel Analog Front-End for EEG Signal Recording on 180nm CMOS Process
  • Citing Conference Paper
  • October 2023

... C. SHA-3 SHA-3 was selected as a result of an open competition organized by the National Institute of Standards and Technology (NIST), with Keccak emerging as the chosen standard. Notably, the standard comprises SHA3-224 [17], SHA3-256 [18], SHA3-384 [19], and SHA3-512 [20]. Keccak primarily integrates sponge functions during the confusion, substitution, and shift phase, thereby enhancing the security of the compression function and allowing for flexible lengths of the output hash value. ...

The Efficiency of High-performance SHA-3 Accelerator on the System Level
  • Citing Conference Paper
  • October 2023