Chunlong Li’s research while affiliated with Chinese Academy of Sciences and other places

Voltage controlled magnetic anisotropy (VCMA) has been considered as an effective method in traditional magnetic devices with lower power consumption. In this article, we have investigated the dual-axis control of magnetic anisotropy in Co2MnSi/GaAs/PZT hybrid heterostructures through piezo-voltage-induced strain using longitudinal magneto-optical Kerr effect (LMOKE) microscopy. The major modification of in-plane magnetic anisotropy of the Co2MnSi thin film is controlled obviously by the piezo-voltages of the lead zirconate titanate (PZT) piezotransducer, accompanied by the coercivity field and magnetocrystalline anisotropy significantly manipulated. Because in-plane cubic magnetic anisotropy and uniaxial magnetic anisotropy coexist in the Co2MnSi thin film, the initial double easy axes of cubic split to an easiest axis (square loop) and an easier axis (two-step loop). While the stress direction is parallel to the [1-10] easiest axis (sample I), the square loop of the [1-10] direction could transform to a two-step loop under the negative piezo-voltages (compressed state). At the same time, the initial two-step loop of the [110] axis simultaneously changes to a square loop (the easiest axis). Otherwise, we designed and fabricated the sample II in which the PZT stress is parallel to the [110] two-step axis. The phenomenon of VCMA was also obtained along the [110] and [1-10] directions. However, the manipulated results of sample II were in contrast to those of the sample I under the piezo-voltages. Thus, an effective dual-axis regulation of the in-plane magnetization rotation was demonstrated in this work. Such a finding proposes a more optimized method for the magnetic logic gates and memories based on voltage-controlled magnetic anisotropy in the future.

In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP oxide + PE TEOS, and (2) PE TEOS + dry etching. Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

The magneto-electric coupling (MEC) effect has been considered an effective method for the voltages controlled magnetic anisotropy in traditional ferroelectric/ferromagnetic structures. Unlike traditional perovskite ferroelectrics, the ferroelectric hafnium-based oxides hold great potential for use in the complementary metal oxide semiconductors (CMOS) circuit with the advantages of CMOS compatibility and easy scaled-down and lower leakage current. In this article, the MEC effects in the PtCoRu/Hf0.5Zr0.5O2 (HZO) heterostructure have been investigated using the polar magneto-optical Kerr effect microscopy and anomalous Hall effect. The major modification of perpendicular magnetic anisotropy of the PtCoRu thin film was controlled obviously within the ±4 V polarized voltages of the Hf0.5Zr0.5O2 (HZO) film, accompanying with the coercivity field and remnant magnetization significantly decreased. The Hall voltages of PtCoRu in Hall bar devices were also controlled effectively under ±3 V polarized voltages. Such a finding proposes a more optimized method for the magnetic logic gates and memories based on voltage-controlled magnetic anisotropy in future.

3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, however, not precise enough for the development of state-of-the-art 3D NAND. In this circumstance, an accurate measurement of dimension for as-formed staircase patterns is of great importance and technical interest. In this paper, an improved measurement method is proposed to meet the requirement for higher precision. By taking the overlay into account, a calculation formula for measuring the dimensional error of as-formed staircase is derived for the first time. Two kinds of anchor design (convex SS0 and concave SS0) are put forward to perform dedicated experiments. Achieved results show that the measurement error of as-formed staircase using this improved method is improved from 31.6 nm for normal measurement method to 14.1 nm. The dimensional uniformity of as-formed staircase is therefore improved significantly which in turn leads to well controlled word line leakage. Furthermore, in advanced staircase structure of stair divided scheme (SDS), the convex SS0 shows an advantage in cost compared to the concave SS0.

Poly-Si channels need well passivated by using hydrogen passivation process in 3D NAND flash memories for better poly-Si quality with low trap density. It is believed that Xtacking 3D NAND flash memory has the advantage of flexible arranging the passivation process. In this article, two different passivation locations were compared in Xtacking structure to achieve better trap passivation. An optimized passivation process conducted at wafer backside with passivation SiN as hydrogen diffusion source was found to have an improved trap passivation result. This benefit was attributed to the sufficient H diffusion paths in Xtacking. These results also indicated the advantage of trap passivation for future higher stacked Xtacking 3D NAND flash memory.

We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Based on the PR consume model, we are able to prove the process efficiency and low cost of SDS. We also show that SDS can improve the integration for higher bit density. Finally, we find that the critical dimension (CD) of stair divided zone shifts post stair etching. We investigate the reason and point out that, it is necessary to make compensation in layout to ensure the precise alignment of stairs.

An effective post etch treatment (PET) process was proposed to eliminate etch damage in the channel hole, of which the depth and the aspect ratio is beyond 3 μm and 30:1 respectively, prior to selective epitaxial growth (SEG) in three dimensions (3D) NAND flash memory. In this work, it is demonstrated that the damaged layer both at the channel hole bottom and sidewall induced by capacitively coupled plasma (CCP) was effectively eliminated using low energy plasma of CL2 + NF3/CH2F2 in PET, and then obtaining an excellent surface condition in channel hole and fabricating a void-free SEG epitaxial layer.

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85°C and –25°C). On the contrary, the low tail of Vth distribution shows a larger shift than the high tail during cross temperature read, after the page programmed under low temperature. The temperature coefficient (Tco) of cell Vth shows cell to cell variations, which can be categorized into two types. For type 1, the Tco is correlated with the selected cell Vth due to polysilicon channel; For type 2, the Tco is independent of the selected cell Vth. The corresponding impacts on Vth distribution are studied via array Monte Carlo simulation. Based on the simulation results, the above temperature dependent observations can be well modeled by the combination of both Tco variation type 1 and 2. Furthermore, two optimization approaches are proposed to alleviate the Vth distribution broadening and are validated by experiments.