Chung-Chih Hung’s research while affiliated with National Yang Ming Chiao Tung University and other places

The 12 articles in this special issue were presented at the 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS) in Toronto, Canada, from October 19–21, 2023. BioCAS 2023 was jointly sponsored by the IEEE Circuits and Systems (CAS) Society, IEEE Solid-State Circuits (SSC) Society, and the IEEE Engineering in Medicine and Biology (EMB) Society.

A CMOS analog front-end (AFE) local-field potential (LFP) chopper amplifier with stimulation artifact tolerance, improved right-leg driven (RLD) circuit, and improved auxiliary path is proposed. In the proposed CMOS AFE LFP chopper amplifier, common-mode artifact voltage (CMAV) and differential-mode artifact voltage (DMAV) removal using the analog template removal method are proposed to achieve good signal linearity during stimulation. An improved auxiliary path is employed to boost the input impedance and allow the negative stimulation artifact voltage passing through. The common-mode noise is suppressed by the improved RLD circuit. The chip is implemented in 0.18- ${{\bf \mu m}}$ CMOS technology and the total chip area is 5.46-mm ² . With the improved auxiliary path, the measured input impedance is larger than 133 M ${\bm{\Omega}}$ in the signal bandwidth and reaches 8.2 G ${\bm{\Omega}}$ at DC. With the improved RLD circuit, the measured CMRR is 131 – 144 dB in the signal bandwidth. Under 60-μs pulse width and 130-Hz constant current stimulation (CCS) with ±1-V CMAV and ±50-mV DMAV, the measured THD at the SC Amp output of fabricated AFE LFP chopper amplifier is 1.28%. The measurement results of In vitro agar tests have shown that with ±1.6-mA CCS pulses injecting to agar, the measured THD is 1.69%. Experimental results of both electrical and agar tests have verified that the proposed AFE LFP chopper amplifier has good stimulation artifact tolerance. The proposed CMOS AFE LFP chopper amplifier with analog template removal method is suitable for real-time closed-loop deep drain stimulation (DBS) SoC applications.

This article presents and demonstrates the design of a high dynamic range (HDR) CMOS image sensor (CIS). Detailed operation of various comparator circuits is analyzed. A low-noise, area-efficient, wide-input range comparator is proposed for HDR applications. Based on the analysis, a six-transistor (6T) comparator is proposed with a p-type metal oxide semiconductor (PMOS) input triplet, which effectively increases the input range of a conventional PMOS-input type comparator and compensates the charge injection and kT/C noise introduced from pixels switching between high-conversion-gain (HCG) and low-conversion-gain (LCG) modes. The proposed scheme achieves an extra high dynamic range (DR). A full HD (1920 $\times$ 1080) HDR image sensor with 2.9 $\mu$ m pixel pitches is fabricated in a 55 nm one-ploy five-metal (1P5M) CIS process. The incorporated analog-to-digital conversion (ADC) demonstrates a 12-bit resolution, a noise of 96 $\mu_{\mathrm{VRMS}}$ , a power consumption of 25 $\mu$ W, an area of 2.9 $\times$ 400 $\mu$ m, and its integral non-linearity (INL) and differential non-linearity (DNL) are $-$ 0.43/ + 7.22 and $-$ 0.30/ + 0.29 LSB, respectively. The sensor achieves a 120-dB DR at 30 frames/sec and a temporal noise of 0.91e-.

The 16 papers in this special issue were presented at the 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS) in Taipei, Taiwan, from October 13–15, 2022. BioCAS 2022 was jointly sponsored by the IEEE Circuits and Systems (CAS) Society, IEEE Solid-State Circuits (SSC) Society, and the IEEE Engineering in Medicine and Biology (EMB) Society.

In this paper, an analog front-end (AFE) local-field potential (LFP) acquisition unit with real-time stimulation artifact removal is proposed and verified for closed-loop deep brain stimulation (DBS) applications. The proposed acquisition unit is called the synchronized sample-and-hold stimulation artifact blanking (SSAB) AFE LFP acquisition unit. Both right-leg-driven (RLD) circuit and monopolar electrode-tissue impedance (ETI) measurement circuit associated with the AFE amplifier are also proposed. During closed-loop stimulations, the artifact removal is realized through the SSAB-IPC by blanking the AR-CCIA with a clock synchronized to the stimulation-enable signal and holding the amplifier at its state before stimulation through a sample-and-hold operation. After stimulation, the acquisition unit can quickly recover from the holding state back to the LFP recording state to reduce the discontinuity in LFP recording. The proposed acquisition unit was fabricated in 0.18-um CMOS technology. With the RLD circuit, the measured CMRR is 124 – 145 dB in the signal bandwidth. The fabricated monopolar ETI measurement circuit has a measurement error less than 8.3% with an extra power consumption of 2.65 $\mu$ W. The experimental results have shown that the proposed SSAB AFE LFP acquisition unit is feasible for the integration of SoCs in real-time closed-loop DBS systems for various applications.

The eight papers in this special issue were presented at the 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS) in Berlin, Germany, from October 6–9, 2021. BioCAS 2021 was jointly sponsored by the IEEE Circuits and Systems (CAS) Society, IEEE Solid-State Circuits (SSC) Society, and the IEEE Engineering in Medicine and Biology (EMB) Society.

Since wearable devices, sensor devices, or implanted devices are powered by batteries, they need to maintain long working time, especially implantable devices, because the battery needs to be replaced by surgery. This chapter introduces how to implement low-power, low-voltage VLSI circuit design. In addition to realizing more transistors in the same area to comply with Moore’s Law, advances in semiconductor technology have also brought many benefits, such as smaller areas, faster speed, more functions, and lower power consumption. From the perspective of technological evolution, there are many compromises in consideration of transistor characteristics. To produce good transistor characteristics, designers must weigh these transistor characteristics to achieve the best design performance or operating point. However, these advanced process nodes have also brought some problems, such as various leakage currents, and battery-powered devices cannot tolerate the waste of electricity. Therefore, we will discuss how to achieve low voltage and low power consumption in digital circuit design, including possible solutions and recommendations, and the trade-offs of reducing dynamic power, static power, and leakage current. Next, we will present the problems faced by low-voltage analog circuit design, and then discuss traditional design methods and gm/ID design methods. Finally, we will discuss some considerations for the design and implementation of nano-analog circuits.

For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This chapter presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-μW power while generating output clock of 401.8–431.31-MHz and exhibiting a phase noise of −105.7 dBc/Hz at 1-MHz frequency offset with 20 μs locking time.