Christopher Lavin’s research while affiliated with Brigham Young University and other places

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Publications (10)


Space-Time Coding for Aeronautical Telemetry: Part II—Decoder and System Performance
  • Article

February 2017

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28 Reads

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19 Citations

IEEE Transactions on Aerospace and Electronic Systems

Michael Rice

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Tom Nelson

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Joseph Palmer

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[...]

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Kip Temple

This paper describes the use of Alamouti-encoded shaped offset QPSK version TG (SOQPSK-TG) to solve the two-antenna problem in aeronautical telemetry. The Alamouti spacetime block code is used to encode the phase states in the complex exponential representation of SOQPSK-TG. Because SOQPSKTG possesses memory, the Alamouti decoder is a sequence estimator. Maximum likelihood and least squares sequence decoders are derived. To reduce the number of states, the 8-waveform cross-correlated trellis-coded quadrature modulation (XTCQM) approximate representation of SOQPSK-TG is used. A prototype decoder based on the least squares decoder and the estimators described in Part I and operating at a data rate of 10 Mbits/s, was tested in the laboratory in test flights at the Air Force Test Center, Edwards AFB. The test flights demonstrate that Alamouti-encoded SOQPSK-TG, as described in this paper using the least squares decoder based on the estimators described Part I solves the two antenna problem in aeronautical telemetry.


Space-Time Coding for Aeronautical Telemetry: Part I—Estimators

February 2017

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56 Reads

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15 Citations

IEEE Transactions on Aerospace and Electronic Systems

This paper derives and analyzes the estimators required for detection and decoding of Alamouti-encoded shaped offset QPSK version TG (SOQPSK-TG). The joint maximum likelihood (ML) estimators for the frequency offset, channel delays, and channel gains are derived and analyzed. As a complexity-reducing technique, a sequential version of the ML estimators is developed. The Cramer-Rao bound for the parameters is derived and used to analyze the performance of the estimators to determine pilot sequence length. The complexity of the frequency estimator is reduced by applying the Zoom FFT algorithm in the coarse search. The complexity of the channel delay estimator was reduced by developing a novel version of the simplex search algorithm that operated on a discrete two-dimensional grid. These estimation algorithms were implemented in a prototype demodulator that was field tested at Edwards AFB.


Improving clock-rate of hard-macro designs

December 2013

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36 Reads

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4 Citations

HMFlow reuses precompiled circuit modules (hard macros) and other techniques to rapidly compile large designs in a few seconds - many times faster than standard Xilinx flows. However, the clock rates of designs rapidly compiled by HMFlow are often significantly lower than those compiled by the Xilinx flow. To improve clock rates, HMFlow algorithms were modified as follows: (1) the router was modified to take advantage of longer routing wires in the FPGA devices, (2) the original greedy placer was replaced with an annealing-based placer, and (3) certain registers were removed from the hard-macro and moved into the fabric to reduce critical-path delays. Benchmark circuits compiled with these modifications can achieve clock rates that are about 75% as fast as those achieved by Xilinx, on average. Fast run-times are also preserved; the improved algorithms only increase HMFlow run-times by about 50% across the benchmark suite so that HMFlow remains more than 30× faster than the standard Xilinx flow for the benchmarks tested in this paper.


Impact of hard macro size on FPGA clock rate and place/route time

September 2013

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27 Reads

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15 Citations

Hard macros are completely placed/routed elements that are treated as primitives and that are relatively placed as a single element. A system composed of such macros consists of many fewer effective primitives and nets and as such can be placed and routed much more quickly. Prior work in this research area dealt with small, general-purpose macros such as 16-bit registers, adders, etc., and demonstrated that place/route time could be reduced by an order of magnitude with a corresponding 3-4X reduction in clock rate. In this work, much larger hard macros are developed such as mixers, softcore processors, FFTs, etc., and the use of these larger macros is shown to further reduce place/route time by an additional 2.5-4X, for a total of a 30-40X reduction in compile time. Clock rate is also improved, relative to earlier work, by an additional 60-70%.


RapidSmith: do-it-yourself CAD tools for Xilinx FPGAs

October 2011

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477 Reads

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110 Citations

Creating CAD tools for commercial FPGAs is a difficult task. Closed proprietary device databases and unsupported interfaces are largely to blame for the lack of CAD research found on commercial architectures versus hypothetical architectures. This paper formally introduces RapidSmith, a new set of tools and APIs that enable CAD tool creation for Xilinx FPGAs. Based on the Xilinx Design Language (XDL), RapidSmith provides a compact, yet, fast device database with hundreds of APIs that enable the creation of placers, routers and several other tools for Xilinx devices. RapidSmith alleviates several of the difficulties of using XDL and this work demonstrates the kinds of research facilitated by removing such challenges.


HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

June 2011

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116 Reads

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89 Citations

The FPGA compilation process (synthesis, map, place, and route) is a time consuming task that severely limits designer productivity. Compilation time can be reduced by saving implementation data in the form of hard macros. Hard macros consist of previously synthesized, placed and routed circuits that enable rapid design assembly because of the native FPGA circuitry (primitives and nets)which they encapsulate. This work presents results from creating a new FPGA design flow based on hard macros called HMF low. HMF low has shown speedups of 10-50X over the fastest configuration of the Xilinx tools. Designed for rapid prototyping, HMF low achieves these speedups by only utilizing up to 50 percent of the resources on an FPGA and produces implementations that run 2-4X slower than those produced by Xilinx. These speedups are obtained on a wide range of benchmark designs with some exceeding 18,000 slices on a Virtex 4 LX200.


Rapid prototyping tools for FPGA designs: RapidSmith

December 2010

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93 Reads

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48 Citations

Designer productivity for FPGA design is significantly limited by the time-consuming nature of the FPGA compilation process (synthesis, map, placement, and routing). However, experimentation on alternative CAD tools for this purpose for Xilinx devices has been somewhat limited. This paper describes the development and distribution of RapidSmith, a software library to facilitate the manipulation of XDL designs and upon which a complete CAD system can be based. The demonstration portion of this paper will show prototypes of representative CAD tools which can be easily built on top of the RapidSmith system.


Using Hard Macros to Reduce FPGA Compilation Time

August 2010

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548 Reads

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19 Citations

The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational effort. Two experiments were performed to demonstrate feasibility that hard macros can reduce compilation time. These experiments demonstrated that an augmented Xilinx flow designed specifically to support hard macros can reduce overall compilation time by 3x. Though the process of incorporating hard macros in designs is currently manual and error-prone, it can be automated to create compilation flows with much lower compilation time.


An FPGA-based Space-time coded telemetry receiver

August 2008

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48 Reads

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3 Citations

The significant problem of data dropouts in aeronautical telemetry due to multiple transmit antennas has escalated as transmit data rates have increased. A proposed solution of using a space-time coded signal can resolve these data dropouts at the expense of increased receiver complexity. This paper describes an implementation overview of an FPGA-based space-time coded telemetry receiver and the various challenges associated with its realization. In addition, we discuss the productivity of the high-level design tool used in constructing the receiver, Xilinx system generator for DSP. With some overhead in terms of FPGA fabric usage and clock speed, our estimates show a 2 - 3x productivity improvement over standard HDLs.


The implementation of an irregular Viterbi trellis decoder

January 2007

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9 Reads

The Viterbi algorithm has uses for both the decoding of convolutional codes and the detection of signals distorted by intersymbol interference (ISI). The operation of these processes is characterized by a trellis. An ARTM Tier-1 space-time coded telemetry receiver required the use of an irregular Viterbi trellis decoder to solve the dual antenna problem. The nature of the solution requires the trellis to deviate from conventional trellis structure and become timevarying. This paper explores the architectural challenges of such a trellis and presents a solution using a modified systolic array allowing the trellis to be realized in hardware.

Citations (9)


... If the same signals are transmitted simultaneously, the received signal could suffer from severe interference due to the considerable phase angle differences between them. This phenomenon is known in aeronautical telemetry [2] as the "two-antenna problem". Jensen et al. showed, in [3], that by applying Alamouti encoding [4], this problem is overcome without the expansion of the re-quired bandwidth. ...

Reference:

A Soft-Output STBC Decoder for Aeronautical Telemetry
Space-Time Coding for Aeronautical Telemetry: Part I—Estimators
  • Citing Article
  • February 2017

IEEE Transactions on Aerospace and Electronic Systems

... Shaped offset quadrature phase shift keying (SOQPSK), a hybrid of OQPSK and MSK, has also attracted wide interest in this literature. Burst-mode synchronisation of SOQPSK for the next-generation aeronautical telemetry system is discussed in [11,12] also uses SOQPSK to solve the twoantenna problem of aeronautical telemetry. Field programmable gate array (FPGA) implementation of SOQPSK for deep-space, telemetry and unmanned aerial vehicle (UAV) links is presented in [13]. ...

Space-Time Coding for Aeronautical Telemetry: Part II—Decoder and System Performance
  • Citing Article
  • February 2017

IEEE Transactions on Aerospace and Electronic Systems

... In addition, some have addressed the challenge from a design methodology's perspective. In [24,25], the authors propose the use of pre-built hard macros and modular design flow to minimize the placement and routing process. A similar approach is also presented in [14] where a library of precompiled macros is constructed for HLS. ...

Improving clock-rate of hard-macro designs
  • Citing Conference Paper
  • December 2013

... In general, when the targeted design has a relatively larger size of hard macro blocks, from the perspective of the implementation time, it could have benefited [20]. However, the functionality and optimization of implemented design with hard macro blocks are guaranteed by the designer rather than a design tool. ...

Impact of hard macro size on FPGA clock rate and place/route time
  • Citing Conference Paper
  • September 2013

... FPGAs are an attractive technology for DSP applications because they are particularly suitable for parallel algorithm implementation. In [7], Lavin et al. described the design of a space-time coded telemetry receiver (SCTR), which can solve the issue of data dropouts due to the use of multiple transmit antennas. Fig. 7 shows a block diagram of this design. ...

An FPGA-based Space-time coded telemetry receiver
  • Citing Conference Paper
  • August 2008

... The XDL offers a textual representation of the placed design, simplifying the retrieval and modification process of the FPGA configurations, which was used in the recent research to reverse engineer the bitstream encoding for AMD Xilinx Virtex-4, 5 devices and older Xilinx FP-GAs [5]- [7]. Also, researchers demonstrated the versatility of XDL by showcasing tasks such as module relocations, duplications, and merging, all of which streamlined the manipulation process prior to generating the final bitstream [8]- [10]. However, we point out that the availability of XDL is only in the Xilinx ISE toolchain which was discontinued in 2013; with the introduction of newer FPGA devices like the Xilinx 7-Series, UltraScale, UltraScale+, and Versal, the industry has transitioned to the Xilinx Vivado toolchain. ...

RapidSmith: do-it-yourself CAD tools for Xilinx FPGAs
  • Citing Conference Paper
  • October 2011

... Electronics 2024, 13, 1100 2 of 16 attack, and tampering with the hardware results in malfunctions, leading to potential damage. Additionally, intelligent reverse engineering [10][11][12][13][14][15][16][17][18][19][20][21] can be utilized to analyze the design of the netlist. When a circuit is attacked, the circuit does not behave as intended, causing serious problems. ...

Rapid prototyping tools for FPGA designs: RapidSmith
  • Citing Conference Paper
  • December 2010

... Previous work has demonstrated that pre-implemented large macroblock components can be an effective approach to reducing FPGA compilation time. HMflow exploited precompilation of hard (internally, pre-placed and routed) macros, macroblock floorplanning, and custom routing to quickly assemble DSP designs from Xilinx's System Generator [12], [13]. Once placed and routed, HMflow uses vendor tools for final bitstream generation. ...

Using Hard Macros to Reduce FPGA Compilation Time
  • Citing Conference Paper
  • August 2010