Christian J. Amsinck’s research while affiliated with North Carolina State University and other places

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Publications (13)


Electronic Properties of Molecular Memory Circuits on a Nanoscale Scaffold
  • Article

January 2008

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99 Reads

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17 Citations

IEEE transactions on nanobioscience

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Fig. 1. Basic process flow: (a) fabricate nanowire array; (b) cover with insulator; (c) open cut in insulator; and (d) fabricate connecting wire array.  
Fig. 2. Demonstration of novelty. As the connecting wires are increasingly " misaligned " from (a) to (c), the system remains one-to-one connected.  
Fig. 3. Connecting wire width versus insulator cut angle () for a nanowire width of 10 nm. The insulator cut angle is governed by the desired application.  
Fig. 4. Rotational misalignment of: (a) the insulator cut (offset from target cut angle is defined as ) and (b) connecting wires (offset from orthogonality is defined as ).  
Fig. 6. Fabrication of proof-of-concept structure. This SEM shows that each vertical connecting wire connects one and only one horizontal "nanowire."

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Deterministic nanowire fanout and interconnect without any critical translational alignment
  • Article
  • Full-text available

August 2006

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56 Reads

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6 Citations

IEEE Transactions on Nanotechnology

Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design

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Physically based molecular device model in a transient circuit simulator

July 2006

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8 Reads

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7 Citations

Chemical Physics

Two efficient, physically based models for the real-time simulation of molecular device characteristics of single molecules are developed. These models assume that through-molecule tunnelling creates a steady-state Lorentzian distribution of excess electron density on the molecule and provides for smooth transitions for the electronic degrees of freedom between the tunnelling, molecular-excitation, and charge-hopping transport regimes. They are implemented in the fREEDA™ transient circuit simulator to allow for the full integration of nanoscopic molecular devices in standard packages that simulate entire devices including CMOS circuitry. Methods are presented to estimate the parameters used in the models via either direct experimental measurement or density-functional calculations. The models require 6 8 orders of magnitude less computer time than do full a priori simulations of the properties of molecular components. Consequently, molecular components can be efficiently implemented in circuit simulators. The molecular-component models are tested by comparison with experimental results reported for 1,4-benzenedithiol.


Scaling constraints in nanoelectronic random-access memories

October 2005

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399 Reads

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79 Citations

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.


Fig. 1. Load line for mononitro dithiol molecule using 1.31G, 575M and 373M resisters.
Fig. 2. Bistable latch for mononitro dithiol molecule loaded with a 373M resister. The two memory states are separated by 0.32 volts.
Molecular electronic latches and memories

August 2005

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62 Reads

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8 Citations

Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to solid state devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A bistable latch and memory architecture are simulated using IV data from the 2'-amino-4-ethynylphenyl-4'-ethynylphenyl-5'-nitro-1-bensenethiolate molecule previously published by the Reed group at Yale University. HSPICE simulation results are used to illustrate the performance of a bistable latch and a memory array.



Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process

July 2005

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86 Reads

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20 Citations

Physica E Low-dimensional Systems and Nanostructures

We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques. (P.D. Franzon).


Cover Picture: An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale (Small 7/2005)

July 2005

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64 Reads

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117 Citations

A three-dimensional bottom-up self-assembly technique is developed to use biomolecules such as DNA as scaffolds. The use of viruses as nanoscale scaffolds for devices provide the exquisite control of positioning on the nanoscale. The efficacy of the approach is tested on 3D conductive molecular networks using cowpea mosaic virus (CPMV) as a scaffold. The conductance of the molecular network self-assembled on a single virus is measured using scanning tunneling microscopy (STM), which shows isolated conductive viral nanoblocks (VNB) attached to a gold substrate through a conducting molecule inserted in an insulating C11 matrix. It is observed that red connections are the least important in the formation of the network, such that their removal decreases the network conductance by just 6% to 94% of the maximum. This bottom-up approach uses different types of molecules for functions such as wires, switches, and diodes to build electronic circuits to increase the theoretical device density.


Molecular Electronics – Devices and Circuits Technology

January 2005

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274 Reads

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4 Citations

IFIP Advances in Information and Communication Technology

Molecular electronics holds significant potential to outscale bulk electronic devices. However, practical issues have limited that potential to date. This paper reviews the function and design of molecular electronics and evaluates results to date in a circuits context.


Discontinuous gold films for nanocell memories

January 2004

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58 Reads

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5 Citations

An important component to the nanocell, among other self-assembled networks, is the fabrication of a framework by which molecular elements can be interconnected. This framework must be nanometric in scale, created in a material suitable for attachment chemistries and remain electrically discontinuous until molecular attachment. Utilizing the Volmer-Weber mechanism by which gold grows on silicon dioxide surfaces, nanometric islands of gold are fabricated to provide this framework. Using standard photolithography techniques, the regions where these islands are located are well defined. A two-layer photoresist stack is developed that prevents edge shorting around the boundaries of each region. The discontinuous gold films fabricated in this study are repeatable, offer a fill factor of 63%, and are easily patterned down to the one-micron scale.


Citations (10)


... Here, we demonstrate the usefulness of this approach by designing , building, and measuring three-dimensional switchable nanoscale molecular networks on a 30 nm diameter cowpea mosaic virus (CPMV) particle. CPMV is an icosahedral particle made of 60 copies of a protein subunit, with a spherically averaged diameter of 30 nm and provides a nanoscale template to generate complex three-dimensional patterns of gold nanoparticles [21]–[23]. CPMV is well-suited for use as a template due to its tolerance of organic solvents, and its stability in pH 3-10 at temperatures up to 70 C. An infectious clone of the virus enables site-directed and insertional mutagenesis to be performed, allowing the production of mutants with specific predetermined patterns of fiunctional groups. ...

Reference:

Electronic Properties of Molecular Memory Circuits on a Nanoscale Scaffold
Cover Picture: An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale (Small 7/2005)
  • Citing Article
  • July 2005

... In this regard, some efforts have been made in order to model molecular electronics [6][7][8][9][10][11]. For electronic devices, in general, there are two major types of models; the physics-based models [10][11][12][13][14], and the nonphysics-based models [15], [16] or behavioral models. Since the underlying physics of molecular electronics have not been yet completely known and also many different kinds of materials are applied in molecular electronics, the behavioral model is more applicable in this field. ...

Physically based molecular device model in a transient circuit simulator
  • Citing Article
  • July 2006

Chemical Physics

... Currently, ebeam lithography, Nanoimprint lithography, step and flash lithography and immersion lithography seems to be the promising candidate for making sub-25 nm nanowires. In our previous work [1] [2] we demonstrated a reliable and costeffective process for making wafer scale sub-25 nm nanowires and nanoimprint molds. The PEDAL technique, although limited to making linear structures, has applications in fabricating high density chemical and biological sensors, crossbar memory structures and high frequency filters and resonators. ...

Wafer scale aligned sub-25nm metal nanowires on Silicon (110) using PEDAL lift-off process

... With some simplifying assumptions, these results showed that it is possible to use nanocells as NAND and XOR gates as well as a 1-bit adder. Later, these authors considered connecting nanocells using bistable latches for signal restoration for logic and memory to determine the viability of programming the nanocells [8], [144]. On the other hand, our group has been involved in the study of the intrinsic characteristics of single molecules to perform programmable functions using high-level quantum chemistry methods and also demonstrating theoretically the possibility of transmission of signals through molecules and the processing of information using MEPs [12], [17]- [20], [86], [90], [96], [97], [106], [110], [111]. ...

Discontinuous gold films for nanocell memories

... However, few processes nowadays exist to overcome lithographic limitation and to fabricate ultra-thin NWs. These techniques include shadow/oblique evaporation [13], guided electrodeposition [14,15] and size reduction lithography, partially performed using atomic layer deposition (ALD) [16][17][18]. The synthesis methods, which are based partially on self-organized or self-assembled mechanisms, e.g., see [19], do typically not use lithographic approaches for dimension and position control. ...

Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process
  • Citing Article
  • July 2005

Physica E Low-dimensional Systems and Nanostructures

... These building blocks possess specific binding capabilities-often termed molecular recognition properties which allow them to arrange automatically in the correct way. Self-assembly is an essential component of bottom-up approaches [22] . Usually bottom-up products have higher purity, better particle size and surface chemistry control. ...

Cover Picture: An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale (Small 7/2005)
  • Citing Article
  • July 2005

... This figure demonstrates that the hysteresis loop exists in the first and third quadrants and passes the (0,0) point; however, the hysteresis graphs have different shapes in general. A survey in the literature was done to find different shapes for hysteresis of molecular devices [18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34], some of which are shown in Fig. 4 with solid line (this figure demonstrates the simulation curves generated from the proposed model in dotted lines, which will be discussed later). All of these graphs obey the two mentioned properties. ...

Electronic Properties of Molecular Memory Circuits on a Nanoscale Scaffold
  • Citing Article
  • January 2008

IEEE transactions on nanobioscience

... Carbon nanotubes have been used in implementing logic and arithmetic circuits such as full adders[7,8], FPGA switches[9], multiple-valued logic circuits[10,11,12], analog and mixed-mode circuits[13]and CNFET-based crossbar memory[14]. Other molecular implementations of memories, latches, and switches have been reported in[15,16]. However, considering these circuits, full adder cell could be more of an interest due to its extensive usage in designing arithmetic circuits[17,18], which are usually located on the critical path of the VLSI systems such as microprocessors. ...

Molecular electronic latches and memories

... This problem is solved using area-distributed interfaces. The idea of achieving CMOSto-nano interface without any 'overlay' alignment using precisely angled cuts, is suggested in [21]. Figure 3 shows the general schematics of a hybrid CMOS/Nano circuit with area distributed interfaces. ...

Deterministic nanowire fanout and interconnect without any critical translational alignment

IEEE Transactions on Nanotechnology