Chien Chung Hung’s research while affiliated with KIIT University and other places

The NBTI characteristics of SiC MOSFET were studied by the subthreshold swing. The subthreshold swing was found to be very sensitive to the starting bias of transfer curve. The increase of subthreshold swing for MOSFET with poor oxide reached 400% when the starting bias was −15 V. The increase of subthreshold swing was caused by enhanced hole trapping which could be explained by the mechanism of positively charged interface states assisted hole trapping. The increase of subthreshold swing for MOSFET with improved gate oxide was reduced to about 40% when the starting bias was −20V and the value approached saturation for starting biases more negative than −10V, which can also be explained by the proposed mechanism. The increase of subthreshold swing for MOSFET with improved oxide was not sensitive to the temperature. The increase of subthreshold swing at 175 T was only 5%∼7% higher than that at room temperature.

MOSFETs and MOS capacitors (MOSCAPs) have been fabricated on Si-face of 4H-SiC to investigate the negative bias temperature instability (NBTI) characteristics of SiC MOSFETs. The shifts of threshold voltage of MOSFETs ranged from -216mV to -1257mV after stressed by 1000sec of -1V to -15V gate bias, correspondingly. The negative shift of the threshold voltage indicated that there were positive charges piled up at or near the oxide/SiC interface. In the mean time, the flat-band voltage shifts of SiC MOSCAPs using the same oxide after stressed by -15V bias for 28800 sec at 175°C were negligible, due to insufficient supply of holes, thus suggesting that the NBTI observed in this study was primarily participated by hole trapping, instead of electron emission. The time evolution of DVth induced by negative bias stress was found to saturate quickly, also suggesting that positive charges were primarily coming from trapping of pre-existing near-interface oxide traps, instead of generation of interface traps. The DVth induced by negative bias stress was lower at higher temperature which might be attributed to faster recovery of hole trapping at elevated temperature.

The influences of positive fixed oxide charges and donor-like interface traps on breakdown voltages of SiC devices with FGR and JTE terminations were studied. The breakdown voltages of devices with both FGR and JTE terminations were found to degrade when the level of fixed oxide charges overs 1×1012 cm-2 due to enhancement of junction curvature by fixed oxide charges. The introduction of donor-like interface traps at the interface shows similar behaviors as fixed positive charges, suggested that both fixed oxide charges and interface traps should be taken into account when one optimizes device designs and processes.

Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C(TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.

SiC lateral MOSFETs with multi-layers epi-channels were studied in this work. The epi-channel with a high concentration n-type epilayer sandwiched by two lightly doped p-type layers showed a maximum field effect mobility of 17 cm2/V.s, improved from 1.53 cm2/V.s of devices without epi-channels. These devices are normally-off with an average threshold voltage of 1.34V.

Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.

One normally-on N-channel AlGaN/GaN device and two types of normally-off GaN devices have been studied. The normally-on device with Sapphire substrate shows good I-dsat and breakdown characteristics, but the gate leakage current is quite large. The first normally-off GaN hybrid metal insulator semiconductor - high electron mobility transistor (MIS-HEMT) grown on Si substrate exhibits good performance with positive threshold voltage of 3V and the breakdown voltage of over 1800V. However the second normally-off GaN MOSFET structure is rather difficult to exhibit good blocking characteristic compared to GaN MIS-HEMT device due to inadequate device design.