C. Senthilpari’s research while affiliated with Multimedia University and other places

Many optimization algorithms were proposed in the past and optimized the distributed generation (DG) in the radial power distribution networks. However, most of the algorithms suffer from poor convergence and local optima stagnation issues due to the complicatedness of the problem. Several new algorithms and enhanced algorithms are recently developed to resolve numerous engineering problems. In this study, an optimization method is developed using the Osprey optimization algorithm (OOA) to determine the best possible solution for the complex DG placement problem. The proposed OOA method optimizes the appropriate size and location for a Type I and III DG to reduce the RDS’s real power losses (RPL). The adequacy of the proposed technique is investigated on the IEEE 33-bus and 118-bus radial PDNs. Furthermore, a real-time Malaysian 54-bus radial PDN is considered to verify the adaptability of the proposed approach. The proposed technique optimized DG placement has minimized the RPL in the IEEE 33-bus radial PDN by 52.47% (Type-I) and 71.95% (Type-III) and likewise, in the Malaysian 54-bus radial PDN the power losses are cut down by 72.56% (Type-I) and 94.88% (Type-III). Moreover, the proposed OOA technique provided better results than the popular and recent optimization techniques cited in literature.

span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

In wireless communication networks, the necessity for high-speed data rates has increased in emerging 5G application areas. The Power Amplifier (PA) topologies reported to date achieved desired Power Added Efficiency (PAE) and linearity. However, these harmonically tuned switching PAs are less appealing for broadband applications as they are restricted to narrow bandwidth (BW). Therefore, to meet the 5G requirements, the challenge of designing a PA with improved efficiency and linearity for a dynamic range of BW becomes critical for PA designers. Recently developed Class-J PA topology can obtain good efficiency while maintaining linearity for wide BW applications. This research work presents a methodology to design a 5 GHz Class-J mode PA topology using Silterra 0.13 μm CMOS technology. This research's main objectives are to determine the R opt of the transistor and design a proper Output Matching Network (OMN) for obtaining Class-J PA operation to make it suitable for 5G wireless applications. The simulation results represent that the designed Class-J PA provides 27 dBm of maximum power output with a maximum power gain of 13.7 dB and the small-signal gain of 17 dB for a BW of around 500 MHz with a 5 V power supply into a 50Ω load.

With higher computerization in the automobile stream, the built-in self-test is essential for high quality and high-reliability SoCs. BIST is a self-testing method for the larger SoC designs. This paper presented a new logic BIST architecture with a new weighted pseudorandom TPG and a hybrid test point allocation method. The proposed architecture is optimized for the physical factors such as the test power consumption, the fault coverage, the WSA, and the area overhead during the scan-in testing phase. The proposed method initiated the sharing concept of flip-flops in the test gate strategies to optimize the area overhead. It also demonstrated the test point allocation enabled using the weighted patterns to enhance the fault coverage throughout the scan chains. The primary seeds are flipped and sorted into weighted patterns to obtain the transition delay faults as their complete fault coverage. Simulation works are examined in SilTerra 0.13 μm on Mentor Graphics IC design tool. Experimental results of the logic BIST architecture are executed, and the results are tabulated. The performance comparison of proposed logic BIST with the existing BIST architectures is also analyzed. Consequently, the proposed BIST is employed in the automobile SoC as an application. The ADAS automobile SoC scan circuits were tested in this paper for their self-testing phenomenon. The tabulated results for the physical factors showed that valuable improvements could be accomplished using the proposed BIST compared with the existing authors.