C. Radens’s research while affiliated with ON Semiconductor and other places

We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um 2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications. I. TECHNOLOGY OVERVIEW The key 7nm technology design features are shown in Table 1. Fin pitch (30nm), contacted gate pitch (56nm), and critical BEOL Mx pitch (40nm) are all significantly scaled compared to the 14nm reference. This enables a strong reduction in the height of the workhorse dense (2-fin) standard logic cell. The overall compaction compared to the 14nm reference is 0.36X across a representative mix of critical cells (i.e. combinational gates, multi-input gates, complex cells, and flip flops). In addition to the dense logic cell, a 4-fin logic cell is also developed for the HPC server space (Fig 1). Whereas the 2-fin logic cell features minimum Mx pitch for height scaling, the 4-fin cell makes use of larger wire dimensions and increased contact sizes to limit IR drop and maximize performance. The performance and power response of 7nm is compared to 14nm in Fig 2. The response illustrates a performance increase of >40% at fixed power, or alternatively power reduction of >55% at fixed frequency. The performance metric accurately represent the FEOL and BEOL RC contributions for a wide range of commercial SoC applications. Also shown in Fig 2 is the performance extendibility achieved by the 4-fin logic cell, which is an important requirement for high-end server applications that focus on single-thread performance. A key enabler for the aggressive scaling in 7nm is the advanced Mx pitch (i.e. M0, M1, M2, M3) achieved through SADP processing. SADP Mx levels are inherently uni-directional, and the dense logic topology has limited resource for wiring. These general aspects add constraints to the routability of a dense logic block. In order to achieve efficient post-route scaling, significant co-optimization is required across both design and technology. For this 7nm technology, a combination of logic cell design, SADP cut placement, pin placement optimization, and general BEOL ground rule optimization are all implemented to increase the utilization levels to the target (Fig 3). While the minimum Mx pitch configuration is critical for density, it is not appropriate for many customized applications (like high speed buffer design or low RC intra-block wiring in large memories). Therefore, the 7nm SADP Mx process has been developed to simultaneously support a large range of wide wires and large contact & vias. The impact of this is illustrated in Fig 4 through the example of a buffer designed for high speed SerDes (HSS) application. Easy integration of wide wires and large contacts is essential for achieving proper voltage swing and transition times in these types of circuits. II. DEVICE ARCHITCTURE AND RELIABILITY In this 3 rd generation fin process, the aggressive 30nm fin pitch is combined with careful fin shaping and fin profile optimization. This leads to direct improvement in the SCE of 7nm devices compared to the 14nm reference (Fig 5). In addition, junction/epi optimization and contact resistance tailoring have all been incorporated to reduce the FinFET parasitic resistance and achieve the target Ieff levels. The impact of targeted process updates is shown in Fig 6. For contact resistance tailoring, trench implantation is introduced to optimize the silicide interface resistance for both NFET and PFET. Cobalt is introduced for contact metallization to reduce the resistance of the 7nm middle-of-line (MOL). A key feature of this 7nm device integration is the 2 nd generation multi-WF process [4] that creates undoped fins for all Vt offerings. A unique workfunction solution is created for 978-1-5386-3559-9/17/$31.00 ©2017 IEEE 29.5.1 IEDM17-689 each FET in the suite from RVt to XLVt (Fig 7). The RVt, LVt, and SLVt devices reflect the standard for most SoC applications. The XLVt is an important addition for HPC application. There are two main benefits of achieving un-doped fins across the entire Vt suite. First, the higher Vt FETs benefit from additional mobility gain in comparison to the reference technology (where fin doping was utilized to create Vt differentiation). Second, the removal of doping improves the RDF and Vt mismatch response fundamentally (Fig 8). The resulting 7nm FET Id-Vg response is shown in Fig 9. The combination of fin profile, junction/epi optimization, contact resistance improvement, and multi-WF gatestack engineering results in excellent subthreshold behavior and a strong transconductance response. The key FEOL reliability modes for this 7nm technology are shown in Fig 10. A comparison to the 14nm reference reflects closely matched defect kinetics for both technologies for gate dielectric TDDB and BTI. The TDDB scales consistently with gate dielectric thickness, and the BTI response reflects a matched time evolution. III. SRAM PERFORMANCE The 7nm 6-T HC and HD bitcell offerings are 0.0353um 2 and 0.0269um 2 , respectively. The previously mentioned multi-WF process and the optimized SCE both have a strong impact on the overall SRAM response (Fig 11). The 7nm technology is demonstrated to have ~2X performance enhancement and >2X the density scaling compared to the 14nm reference. The companion SNM characterization reflects a margin of 100mV at 0.6V, and 72mV at 0.45V (Fig 12).A shmoo plot of a 32Mb HC memory array shows read and write operation down to 0.5V (Fig 13). IV. BEOL AND COMPONENTS Multiple Cu/LowK BEOL stacks are offered to enable a range of SoC applications. An example of a general purpose 13-level stack is given by 1X (M0-M3), 2X (M4-M9), 3.2X (M10,M11), and 18X (M12,M13). A cross section of this stack (focusing on the densest 1X and 2X levels) is shown in Fig 14. Variants with 6.4X, 9X, and 60X ultra thick levels are also available for large HPCs or ASICs with more demanding power distribution requirements. Due to the highly scaled Mx minimum pitch, the capacitance contribution from those BEOL levels is generally the highest (for a standard logic block). Therefore, capacitance reduction for Mx levels is particularly valuable. In this 7nm technology, Mx capacitance reduction is achieved from the optimization of both the low-K fill and the etch stop layer. The resulting improvement in the RC response is shown in Fig 15. In addition, the Mx metallization process has been updated to significantly improve the electromigration (EM) lifetime for minimum Mx wires (Fig 16). The 7nm technology incorporates a number of key component-level enhancements across the suite of device and passive elements. A few examples are reviewed in Fig 17. An advanced BEOL MIMcap is available in 7nm for applications where strong power supply decoupling is required. This enhanced structure delivers a significant capacitance density increase (~2X) over the previous MIMcap in the 14nm reference (Fig 17a). An improved MOScap unit cell is also available in 7nm for general decoupling needs (Fig 17b). This structure's capacitance density improvement (~1.6X) is related to two main technology features: i) the aggressive scaling of fin pitch and ii) the reduced gate to gate space for long channel MOScap structures. These scaling features are also applicable to high voltage (thick oxide) drivers commonly used in GPIOs or DDR interfaces. A reduced area ESD protection device is also present in 7nm (Fig 17c). The footprint reduction (~0.6X) is enabled by an improved diode I-V response and a lower turn-on voltage (Fig 18). The improvement to the junction is achieved within the scope of the base process. V. EUV FOR HVM EFFICIENCY This 7nm technology is enabled by immersion lithography. For the Vx via and contact levels, multi-patterning is required to support the aggressive pitches and the dense logic cell. For these specific MP via and contact levels, EUV has been enabled to reduce the cycle time and improve high volume manufacturing (HVM) efficiency. An example of EUV patterned contacts is shown in Fig 19. This strategic EUV insertion lowers the overall mask count of critical layers by ~25%. No design update is required to take advantage of this EUV insertion. VI. CONCLUSIONS We present a leadership 7nm CMOS technology that reflects significant density scaling and performance over 14nm. A complete set of foundation and complex IP is available to enable both HPC and mobile applications. In addition, a high performance ASIC design system and services offering is available that leverages the 7nm technology and IP platform. ACKNOWLEDGMENT

This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um₂ cell.

The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm² SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

In this work, we have conducted a systematic investigation of leakage current and reliability for re-oxidized nitride, both in planar films and deposited in the deep trenches for DRAM storage-capacitor applications. It was found that for the same equivalent thickness (Teq), the leakage current of re-oxidized nitride is anomalously higher than that of SiO₂. We demonstrate that this increase in leakage current is caused by a reduction of oxide barrier height from -3 eV to -2.2 eV. In addition, the species release and injection process at the anode, by the energetic electrons, is greatly enhanced by the barrier-height reduction. Within the framework of the current understanding of oxide breakdown, this reduction in oxide barrier-height can self-consistently explain the breakdown data in reoxidized nitride films in many aspects: 1) T_BD polarity and thickness dependence; 2) the disappearance of T_BD polarity dependence for thinner films; 3) a much stronger T_BD (Q_BD) thickness dependence causing a crossover effect in comparison with SiO₂. This result suggests that the defect generation rate in reoxidized nitride is thickness dependent. Using a cell-based analytical model, we found that the critical defect density at breakdown extracted from the thickness dependence of Weibull slopes is higher than SiO₂. The similarities and differences in T_BD (Q_BD) voltage- and temperature dependences between reoxidized nitrides and silicon dioxides are discussed. As compared to reoxidized nitride, it is shown that high quality SiO₂ can offer a thickness scaling option for storage capacitors assuming silicon dioxide can be successfully fabricated in deep trenches with sufficiently low defect density as required by DRAM applications.