Bongjin Kim’s research while affiliated with Korea Advanced Institute of Science and Technology and other places

This work proposes the Poisson equation formulation of the Retinex model for image enhancements using a low-power graph hardware accelerator performing finite difference updates on a lattice graph processing element (PE) array. By encapsulating the underlying algorithm in a graph hardware structure, a highly localized dataflow that takes advantage of the physical placement of the PEs is enabled to minimize data movement and maximize data reuse. The on-chip dataflow that achieves data sharing, and reuse among neighboring PEs during massively parallel updates is generated in each PE driven by two external control signals. Using a custom accumulator design intended for bit-serial computing, this work enables precision on demand and extensive on-chip data reuse with minimal area overhead, accommodating a non-overlap image mapping scheme in which a 20×20 image tile can be processed without external memory access at a time. With increasing user-configurable update count, image noise and shadow can be progressively removed with the inevitable loss of image details. Fabricated using a 65nm technology, the test chip occupies 0.2955mm² core area and consumes 2.191mW operating at 1V, 25.6MHz, and a reconfigurable 10-or 14-bit precision.

Combinatorial optimization problems (COPs) are essential in various applications, including data clustering, supply chain management, and communication networks. Many real-world COPs are non-deterministic polynomial-time hard problems intractable using classical computers. Ising machine, the hardware accelerator based on the Ising model and annealing operation, has gained much attention as an alternative for solving COPs. The COPs are mapped to the Ising model, and their optimal/near-optimal solutions are explored by the intrinsic convergence property of the Ising machine. However, prior Ising machines based on locally connected spins have limitations in solving hard COPs due to significant overhead while mapping the Ising model to the inflexible hardware topology. In this work, we propose a scalable CMOS Ising machine with a network of flexible processing elements (PEs) to map and solve complex COPs with minimal overhead. The proposed Ising machine implements 256 PEs, where each PE is reconfigured to 1-to-4 spins with 28 spin interactions based on 8-bit coefficients. A 65-nm prototype chip has been fabricated, and a range of COPs have been mapped and solved, including max-cut and Boolean satisfiability problems.

This article presents a novel dual 7T static random-access memory (SRAM)-based compute-in-memory (CIM) macro for processing quantized neural networks. The proposed SRAM-based CIM macro decouples read/write operations and employs a zero-input/weight skipping scheme. A 65nm test chip with $528\times 128$ integrated dual 7T bitcells demonstrated reconfigurable precision multiply and accumulate operations with 384 $\times$ binary inputs (0/1) and $384\times 128$ programmable multi-bit weights (3/7/15-levels). Each column comprises 384 $\times$ bitcells for a dot product, 48 $\times$ bitcells for offset calibration, and 96 $\times$ bitcells for binary-searching analog-to-digital conversion. The analog-to-digital converter (ADC) converts a voltage difference between two read bitlines (i.e., an analog dot-product result) to a 1-6b digital output code using binary searching in 1-6 conversion cycles using replica bitcells. The test chip with 66Kb embedded dual SRAM bitcells was evaluated for processing neural networks, including the MNIST image classifications using a multi-layer perceptron (MLP) model with its layer configuration of 784-256-256-256-10 The measured classification accuracies are 97.62%, 97.65%, and 97.72% for the 3, 7, and 15 level weights, respectively. The accuracy degradations are only 0.58 to 0.74% off the baseline with software simulations. For the VGG6 model using the CIFAR-10 image dataset, the accuracies are 88.59%, 88.21%, and 89.07% for the 3, 7, and 15 level weights, with degradations of only 0.6 to 1.32% off the software baseline. The measured energy efficiencies are 258.5, 67.9, and 23.9 TOPS/W for the 3, 7, and 15 level weights, respectively, measured at 0.45/0.8V supplies.

This work presents a digital hardware accelerator with compute-near-memory to solve 2-D and 3-D partial differential equations (PDEs) using the finite difference method (FDM). The proposed hardware accelerator is reconfigured to solve 2-D/3-D Laplace and Poisson equations, and it scales to solve larger 2-D problems with no additional overhead. The reconfigurable and scalable architecture is implemented by building a 16 $\times$ 16 near-memory bit-serial processing element (PE) array and four 16 $\times$ boundary PEs with 92-kb static random-access memory (SRAM) distributed in the PE array. The proposed near-memory bit-serial computing architecture reduces data movement and achieves higher energy efficiency than the conventional Von Neumann architecture. The bit-serial computing architecture allows the PEs to communicate with neighbors via a minimal communication bandwidth (1 bit). The proposed hardware accelerator finds numerical solutions to 2-D PDEs (with up to a 64 $\times$ 64 grid size) and 3-D PDEs (with up to a 16 $\times$ 16 $\times$ 16 grid size) using FDM. A prototype chip is fabricated using 65 nm, occupying a 1.78-mm $^{{2}}$ die area. The measured energy to solve the 2-D/3-D PDE for updating an entire grid is 0.7 nJ/1.14 nJ at 1 V and 25.6 MHz.

This work presents a hardware accelerator realizing true time-domain wavefront computing in a massive parallel two-dimensional (2-D) processing element (PE) array. The proposed 2-D time-domain PE array is designed for multiple applications based on its scalable and reconfigurable architecture. The shortest path problem (a classical problem in graph theory) is one of the critical problems to solve using the proposed accelerator. Unlike the A ${}^\ast$ search algorithm, a heuristic method widely used in shortest path searching problems, the proposed accelerator requires only the propagation of rising-edge signals through the PE array without calculating or estimating the distances from the start to the goal. Hence, a single execution of the proposed time-domain wavefront computing provides all the optimal paths from a start point to an arbitrary goal. Besides the King’s graph model used for solving the shortest path searching, the PE array is reconfigured to a simpler lattice graph model and solves other problems, such as maze solving we used in this article as a benchmark. In addition, we used the proposed accelerator to demonstrate a scientific simulation. The propagation of circular or planar wavefronts was simulated using single or multiple start points using King’s graph configuration. A 1 $\times$ 1 mm $^{2}$ test chip with a 32 $\times$ 32 reconfigurable time-domain PE array is fabricated using a 65-nm process. For a 2-D map with 32 $\times$ 32 vertices, the proposed PE array consumes 776 pJ per task and achieves 1.6 G edges/second search rate using 1.2-/1.0-V core supply voltages.