Bin Song’s research while affiliated with University of Electronic Science and Technology of China and other places

The hybrid continuous modes are constituted by a continuum of power amplifier (PA) modes between class-J and continuous class-F. In this letter, a phase shift parameter is introduced in the voltage waveform formula of the hybrid continuous modes to generate complex fundamental and harmonic load impedances, leading to a further extension on the operation bandwidth. Based on the proposed theory, a gallium nitride PA is designed and fabricated over the frequency band of 1.2-3.6 GHz. The measured results show a 60%-72% drain efficiency at a saturated power of 40-42.2 dBm. In addition, when driven by a 20-MHz long-term evolution signal with a peak-to-average power ratio of 7.4 dB, the proposed PA obtains an adjacent channel leakage ratio of -35 dBc at an average output power of 35 dBm at 2.3 GHz.

This paper proposes a harmonic efficiency selectivity circuit (HESC) for achieving a broadband Class-J/F⁻¹ continuum mode power amplifier (PA) with enhanced efficiency. Design equations are derived through continuum mode condition analysis and are used in implementing the HESC. The implemented HESC topology is then used in attaining the broadband Class-J/F⁻¹ continuum mode PA. A theoretical parameter termed harmonic-alpha (ρh) acting as a sub-unit structure in HESC is introduced. Considering harmonic losses, ρh possesses a lookup table containing information on the harmonics. ρh operates in unison with the HESC in selecting the suitable harmonics with the best efficiencies. With ρh, the relationship among the HESC, the optimal impedance at the device’s drain, and the terminal load impedance is defined for a greater freedom of harmonic impedance solutions space, efficiency improvement, and bandwidth extension, thus, indicating an increased flexibility in the design of broadband continuum mode PAs. This method is validated with a realized PA prototype operating from 1.3 to 2.4 GHz corresponding to a fractional bandwidth of 59.5%. The experimental results under continuous wave signals indicate that 79% peak efficiency, 42.68 dBm peak output power, and 16.96 dB peak gain are recorded. Moreover, at 1.7 GHz, when being tested with modulated signals at an average output power of 34.83 dBm, the lower and higher adjacent channel power ratios (ACPRs) without digital predistortion (DPD) are −34.9 dBc and −33.9 dBc, respectively, and a drain efficiency (DE) of 45% is recorded. With DPD, −50.8 dBc and −50.3 dBc are respectively obtained at lower and higher ACPRs at an average output power of 34.6 dBm, and a DE of 44% is achieved.

In this paper, a broadband continuous-mode Doherty power amplifier (CM-DPA) is realized taking advantage of the noninfinity output impedances of peaking stage. Specifically, the carrier PA of the designed DPA operates in a continuous class-J mode when the peaking PA is in the OFF-state, where the output impedance of the peaking PA has some influences on the carrier PA. When the peaking transistor is in the OFF-state, the load impedance variation of the carrier transistor versus noninfinity peaking impedance is presented in this contribution. The proposed method surmounts the back-off drain efficiency deterioration of DPAs at two side working bands through elaborately processing the noninfinity peaking impedance. This paper also presents a method to derive the required OFF-state output impedance of the peaking stage by the carrier PA in a symmetrical broadband DPA. A broadband CM-DPA working over 1.6-2.7 GHz (bandwidth of 51%) is designed and fabricated for interpreting our theories. The simulated load trajectory of the carrier transistor is in line with the design space of continuous class-J mode. Under continuous wave excitation, experimental results show the drain efficiencies of 46.5%-63.5% at 6-dB output back-off power levels and 56%-75.3% at peaking power levels. The maximum output power of this DPA is 43.8-45.2 dBm with a gain of 9.4-11.5 dB across the whole working band. Furthermore, a 20-MHz LTE modulated signal with a peak-to-average power ratio of 7.4 dB is also applied to the fabricated CM-DPA at 2.2 GHz. At an average output power of 37.5 dBm, measurement results show the adjacent channel power ratios of -30.2 and -50.1 dBc before and after digital predistortion, respectively.

A dynamic deviation memory polynomial (DDMP) model for digital predistortion is proposed to compensate the non-linear distortion of the power amplifier. It is based on the memory polynomial model and dynamic deviation reduction-based Volterra (DDRV) model. Compared to the DDRV model, the proposed model shows better modelling accuracy under the same complexity. The effectiveness of the DDMP model has been verified by simulation and experiment results.