B. Aspar’s research while affiliated with Atomic Energy and Alternative Energies Commission and other places

A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

This invention provides composite semiconductor substrates and methods for fabricating such substrates. The composite structures include a semiconductor substrate, a semiconductor superstrate and an intermediate layer interposed between the substrate and the superstrate that comprises a material that undergoes a structural transformation when subject to a suitable heat treatment. The methods provide such a heat treatment so that the intermediate layer becomes spongy or porous, being filled with numerous micro-bubbles or micro-cavities containing a gaseous phase. The composite semiconductor substrates with structurally-transformed intermediate layers have numerous applications.

The advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart‐Cut® SOI process used for the manufacture of the Unibond® SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart‐Cut® process is described in detail and material characteristics of Unibond® wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

Wafer stacking technologies are today available for different D integration schemes. These are compatible with back end of line CMOS processes and packaging. Smart Stacking technology and copper to copper direct bonding processes were described as key technologies to realize dielectric or metallic bonding at room temperature and without applied pressure and/or additional glue layer. This results in a low stress stacked structure enabling high yield post process. Low temperature Smart Cuttrade is a third way to build 3D structures and bring opportunity to relax some stringent alignment constraints.

The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.

The need for high-frequency, wide-band filters has instigated many developments based on combining thin piezoelectric films and high acoustic velocity materials (sapphire, diamond-like carbon, silicon, etc.) to ease the manufacture of devices operating above 2 GHz. In the present work, a technological process has been developed to achieve thin-oriented, single-crystal lithium niobate (LiNbO3) layers deposited on (100) silicon wafers for the fabrication of radio-frequency (RF) surface acoustic wave (SAW) devices. The use of such oriented thin films is expected to favor large coupling coefficients together with a good control of the layer properties, enabling one to chose the best combination of layer orientation to optimize the device. A theoretical analysis of the elastic wave assumed to propagate on such a combination of material is first exposed. Technological aspects then are described briefly. Experimental results are presented and compared to the state of art.

Direct Wafer Bonding has been widely developed and is very attractive for a lot of applications. Using original techniques based on direct bonding enable to carry out specific engineered substrates. Various illustrations are given among which twisted Si-Si bonded substrates, where buried dislocation networks play a key role in the subsequent elaboration of nanostructures.

In microelectronics and MEMS (micro electro mechanical systems) industries, complex structures are required to improve IC's performance or to achieve high levels of integration. The level of integration is now so important that we are talking more and more about systems. Different approaches have been developed to obtain such a system. "System in package" relies on the association in a same package of several dies built on different technologies. "System on chip" integrated on single chip different functions or components often built on a similar technology. This limits the possibility of integrating circuits which perform with various technologies. Further integration requires reliable and cost effective solutions for 3D structures allowing ultimately stacking of various IC's on a chip. In this context, direct wafer bonding appears as a key generic technology to increase systems integration but also to achieve original structures difficult to obtain by other methods. Transfers of partially or fully processed layers onto different supports offer plenty of solutions for the fabrication of new structures. Recent results obtained by wafer bonding and thinning down techniques are presented in this paper