Asen Asenov’s research while affiliated with University of Glasgow and other places

In this paper, we look at how artificial neural networks (ANNs) may be used to improve compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and how it can be applied to 6NST-static random access memory (SRAM) simulations. To begin, both the TCAD simulation platform and compact model of 3D n-type and p-type NST have been rigorously validated against the experimental data. The transfer characteristics curves of 1104 NST samples generated by metal gate granularity, random discrete dopants and line edge roughness are used to extract the important figures of merit (FoM) including ON-current (I ON), OFF-current (I OFF), threshold voltage (V TH) and subthreshold slope. Meanwhile, we can collect the main compact model parameters of these NST samples using our automatic extraction technique. Furthermore, a multi-layer ANN engine is trained to anticipate the important compact model parameters by entering FoMs, which significantly speeds up the automatic extraction. When we compare the prediction results to the genuine values, we discover that their correlation coefficients are all larger than 0.99. Finally, we simulated the 6NST-SRAM circuit and obtained its stability variation, with the help of extracted NST variability by the aforementioned speedup techniques.

The beneficial characteristics of polyoxometalate (POM) molecule-based flash memory cells provide interesting opportunities for scaling beyond the limitations of conventional flash cells. In this paper, we study the write, erase, and retention times of POM flash cells using a kinetic Monte Carlo method implemented in the multi-scale Nano-Electronic Simulation Software simulation framework. The POM flash structure is optimized by studying the tradeoffs between program/erase time and retention time. Based on the optimized POM flash structure, the POM molecular layer charging and discharging processes as well as the corresponding threshold voltage variation are analyzed. The distributions of write, erase, and retention times are simulated and analyzed when studying the POM flash dynamic charging and discharging characteristics.

The implementation of a source to drain tunneling in ultrascaled devices using MS-EMC has traditionally led to overestimated current levels in the subthreshold regime. In order to correct this issue and enhance the capabilities of this type of simulator, we discuss in this paper two alternative and self-consistent solutions focusing on different parts of the simulation flow. The first solution reformulates the tunneling probability computation by modulating the WKB approximation in a suitable way. The second corresponds to a change in the current calculation technique based on the utilization of the Landauer formalism. The results from both solutions are compared and contrasted to NEGF results from NESS. We conclude that the current computation modification constitutes the most suitable and advisable strategy to improve the MS-EMC tool.

In this paper, the stability of static random access memory (SRAM) under the influence of statistical variability and bias temperature instability (BTI) induced ageing is investigated by statistical simulations. Effectively infinite and accurate compact models are successfully generated using ModelGenTM technology to prevent subsampling problem and ensure the statistical SRAM investigation, which successfully present device simulation results for circuits. The impact of transistor’s statistical variability on the SRAM stability is evaluated by SRAM static noise margin (SNM) sensitivity test. Three BTI induced ageing patterns of the SRAM cell are analysed at different ageing levels. The distribution, increase and decrease percentage of SNM is calculated at statistical level to show the combined effects of transistors’ variability with different ageing pattern.

This article presents an accurate, reliability-aware statistical Berkeley short-channel IGFET Model 4 (BSIM4) compact model parameter generation methodology using the generalized lambda distribution (GLD) method. Using this methodology, compact model parameter sets can be generated “on the fly” beyond the limitation of the number of compact models extracted from the TCAD simulation. The generated unlimited parameter sets enable circuit designer for the statistical circuit simulation. An analytical model has been developed to interpolate TCAD simulation data points, which enables statistical compact model parameter sets to be generated at any aging level. The capability to generate such intermediate aging model parameters at trap densities that were not physically simulated has important application in statistical circuit simulation, opening up the possibility to include accurately reliability assessment in circuit design. An aging model that can transfer trap density to stress/aging time is an integral part of the presented methodology. The accuracy of the compact model parameter generation methodology is validated by comparing the new generated compact model parameter sets at an interpolated trap density, against physical “atomistic” 3-D TCAD simulation. The compact model parameter generation methodology enables the accurate investigation of the influence of statistical variability and bias temperature instability (BTI)-induced aging at circuit level.

Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive three-dimensional (3D) structure-aware Rsd compact model is developed and comprehensively validated in respect of 7nm bulk FinFET TCAD platform. Our TCAD model were calibrated against GlobalFoundries/Samsung 7nm FinFET technology experimental data and further validated by two-dimensional (2D) Poisson-Schrodinger simulation. Verilog-A coded SPICE Rsd compact model coupled with proper transport models, indicates that the degradation of saturation current as well as the proportion of Rsd to total device resistance continues to increase from 45% to 49% and 52% with the scaling of the FinFET from 7nm to 5nm and 3nm FinFETs, with errors of less than 4%. TCAD and compact model simulation results both show that the extension and epitaxial contact regions become dominant while metal contact resistivity can be reduced below 6~8 ×10-9 Ω.cm2.

In this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate length MOSFETs, typical for 20 nm bulk CMOS technology, are used as test-bed transistors to illustrate our approach. Statistical physical simulations of fresh devices and devices at initial, middle and final stages of BTI degradation are performed and the corresponding nominal and statistical compact models are extracted using a two-stage extraction strategy. The extracted compact models not only accurately capture time evolution of the statistical distribution of the key MOSFET figures of merit, but also the complex correlations between them. An excellent agreement with the original physical TCAD simulation results provides a high degree of confidence that the extracted compact models deliver accurate representation of the operation of each device for the purposes of reliable circuit simulation and verification.

In this letter, we report a quantum transport simu- lation study of the impact of Random Discrete Dopants (RDD)s on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s func- tion formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD induced ON-current variations in conventional CMOS transistors, the TFET’s ON- currents variations are described by a logarithmic distribution. The distributions of other Figures of Merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analysed by studying the correlation between the number and the position of the dopants. IEEE