Aaron Voon-Yew Thean’s research while affiliated with National University of Singapore and other places

Antiferromagnets hosting real-space topological textures are promising platforms to model fundamental ultrafast phenomena and explore spintronics. However, they have only been epitaxially fabricated on specific symmetry-matched substrates, thereby preserving their intrinsic magneto-crystalline order. This curtails their integration with dissimilar supports, restricting the scope of fundamental and applied investigations. Here we circumvent this limitation by designing detachable crystalline antiferromagnetic nanomembranes of α-Fe2O3. First, we show—via transmission-based antiferromagnetic vector mapping—that flat nanomembranes host a spin-reorientation transition and rich topological phenomenology. Second, we exploit their extreme flexibility to demonstrate the reconfiguration of antiferromagnetic states across three-dimensional membrane folds resulting from flexure-induced strains. Finally, we combine these developments using a controlled manipulator to realize the strain-driven non-thermal generation of topological textures at room temperature. The integration of such free-standing antiferromagnetic layers with flat/curved nanostructures could enable spin texture designs via magnetoelastic/geometric effects in the quasi-static and dynamical regimes, opening new explorations into curvilinear antiferromagnetism and unconventional computing.

Analog resistive random access memory (RRAM) devices enable parallelized nonvolatile in-memory vector-matrix multiplications for neural networks eliminating the bottlenecks posed by von Neumann architecture. While using RRAMs improves the accelerator performance and enables their deployment at the edge, the high tuning time needed to update the RRAM conductance states adds significant burden and latency to real-time system training. In this article, we develop an in-memory discrete Fourier transform (DFT)-based convolution methodology to reduce system latency and input regeneration. By storing the static DFT/inverse DFT (IDFT) coefficients within the analog arrays, we keep digital computational operations using digital circuits to a minimum. By performing the convolution in reciprocal Fourier space, our approach minimizes connection weight updates, which significantly accelerates both neural network training and interference. Moreover, by minimizing RRAM conductance update frequency, we mitigate the endurance limitations of resistive nonvolatile memories. We show that by leveraging the symmetry and linearity of DFT/IDFTs, we can reduce the power by 1.57 $\times$ for convolution over conventional execution. The designed hardware-aware deep neural network (DNN) inference accelerator enhances the peak power efficiency by 28.02 $\times$ and area efficiency by 8.7 $\times$ over state-of-the-art accelerators. This article paves the way for ultrafast, low-power, compact hardware accelerators.

The thermal conductivity measurement of films with submicrometer thicknesses is difficult due to their exceptionally low thermal resistance, which makes it challenging to accurately measure the temperature changes that occur as heat flows through the film. Thus, specialized and sensitive measurement techniques are required. 3ω method is a widely used and reliable tool for measuring the thermal conductivity of films. However, the high in-plane thermal conductivity in thin films results in rapid heat dissipation across the thin film, resulting in poor measurement sensitivity and making it difficult to accurately measure the temperature gradient with the traditional 3ω method. Also, the traditional 3ω method requires cross-plane thermal conductivity to derive the in-plane counterpart. Here, we introduce a dual-domain 3ω method that adopts AC-modulated heating and electrode arrays facilitating surface temperature profiling: (1) the sensitivity was significantly improved due to the employment of low-thermal-conductivity-substrate, and (2) cross-plane thermal conductivity is not required for the analysis of in-plane counterpart. This measurement platform allows us to control heat penetration in depth via varied heating frequencies as well as spatial temperature detection through laterally distributed electrodes on the thin film surface. By utilizing the described method, we have determined the in-plane thermal conductivity of a copper film, having a thickness of 300 nm, which was found to be 346 Wm−1K−1 and validated by the Wiedemann–Franz law.

In recent years, heterogeneous integration (HI) has become a game-changing technology for the construction of complex photonic integrated circuits. Comparing to monolithic integration (MI) technique, chips are stacked or add-on during HI. These components are attached to the substrate using an active or passive alignment scheme. As the passive alignment system does not actively search for the optical axis, it allows more die to be bonded per unit time as compared to active alignment. The main challenge is then to obtain consistent sub-micron alignment accuracy during chip manufacturing process to ensure good device performance. To achieve sub-micron alignment accuracy, slide-stop structures with multi-axial elastic averaging coupling designs are implemented. In this work, optical dies are bonded to silicon interposers with two geometrically different slide-stop designs: triangle and rectangle in designs, respectively. Due to an additional surface contact and smaller internal angle for the former, the triangle slide-stop design improves the translational-axes and rotational-axis post-bond alignment accuracy, from (Reference) −0.27 μm ± 2.54 μm @ 3sigma to (slide-stop) −0.09 μm ± 1.37 μm @ 3sigma, (Reference) 1.00 μm ± 3.19 μm @ 3sigma to (slide-stop) 0.39 μm ± 1.29 μm @ 3sigma, and (Reference) 0.06° ± 0.34° @ 3sigma to (slide-stop) 0.0002° ± 0.15° @ 3sigma respectively. Finally, narrower optical power output distribution of P-down bonded lasers with triangle slide-stop over lasers with rectangle slide-stop is demonstrated.