A. Nomura’s research while affiliated with Aichi Medical University Hospital and other places

The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.

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We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65μm² SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Background Although cholesterol management reportedly reduces fatal and non-fatal coronary heart disease (CHD) events in subjects with or without evident atherosclerotic disease, it is still uncertain whether these benefits extend to Japanese. Methods and Results The study group comprised 8,009 subjects with mildly elevated total cholesterol who were randomized to treatment with 10-20 mg pravastatin plus diet (2,691 women, 1,267 men) or diet alone (2,758 women, 1,293 men). The groups were extremely well balanced with respect to baseline demographics and risk factors such as blood pressure and plasma lipids. Over a 5-year period of follow-up, the primary end-points will be a composite of fatal and non-fatal coronary events. Secondary end-points will include stroke and transient ischemic attack, all cardiovascular events and total mortality. Conclusions The 2 groups will be followed up until the end of March 2004 and end-points will be analyzed by full analysis set.