A. Bonetto’s research while affiliated with Politecnico di Milano and other places

Mobile devices, due to their wide distribution and to their increasing smartness and availability of computational power, can become the interaction point between users and their surrounding environments. However, current mobile devices OSes lack of the ability to anticipate and overcome internal and external changes. Integrating mechanisms of self-awareness and self-adaptability in nowadays smartphones is an attractive perspective to match with these requirements. Moreover, adaptive behaviors can enhance the management by the mobile device itself, of the available resources at its best, e.g., the battery life. This paper envisions various situations in which a self-aware mobile device can interact with the surrounding environment and support the user in performing everyday actions. A prototype of such an adaptive device, called morphone.os and based on the Android OS, has been designed and implemented to verify the reaction of the device in different situations providing convincing and promising preliminary results.

Due to their wide distribution and their growth in functionalities, mobile devices are the interaction point between users and the surrounding environment. Nevertheless, their resources are limited and variable over time, both in terms of performance and power. Especially when dealing with power consumption, mobile devices cannot disregard the environment conditions and the user habits. To manage at the best one of the most important mobile device resource, battery lifetime, we are proposing MPower, an adaptive power management system for Android based mobile devices. The ultimate goal of this research is to automatically generate and select user-specific power profiles, to best optimize the device power consumption given the device features, the environmental conditions and the user needs. MPower is a project currently under development and this paper aims at presenting the overall vision of the research, focusing on the data collection phase, which is a central activity to fulfill the proposed objectives.

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.

Nowadays, the usual embedded design flow makes use of different tools to perform the several steps required to obtain a running application on a reconfigurable platform. The integration among these tools is usually not fully automated, forcing the developer to take care of these intermediate steps. This process slows down the application development and delays its time to market. In this work we present the TaBit framework, intended for FPGA designers, that is able to guide the developer from the original partitioned application, described as a task graph, down to its deployment onto the target device. Moreover, this framework defines a set of interfaces that allows the developer to integrate custom scheduling and floor placing techniques. The framework takes care of the integration between the different steps and, based on the designer inputs, it is able to automatically generate a software Scheduling Engine and the set of bitstreams ready to be deployed onto the target device.

Partial dynamic reconfiguration of FPGAs is a methodology that allows the efficient use of FPGAs resources and an improved degree of flexibility with respect to static hardware when designing an architecture on FPGA. Recently several tools, aiming at supporting the designer in the implementation and the validation processes involved in partial reconfiguration, have been released. Within this scenario we introduce a framework, called ReBit, intended to be complementary to the most important of tool suite available today, e.g. Xilinx ISE suite, improving the existing features and adding new ones, such as partial bit stream scheduling policy testing and algorithmic bus macros placement, using different APIs, integrated in the framework. These features have been validated using different Xilinx FPGAs Spartan 3, Virtex II Pro and Virtex 4.