[Show abstract][Hide abstract] ABSTRACT: We have proposed an integrated method to realize MLC PRAM at 45 nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.
[Show abstract][Hide abstract] ABSTRACT: Advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond
[Show abstract][Hide abstract] ABSTRACT: Advanced bottom electrode contact (BEC) scheme was successfully developed for fabricating reliable high density 64 Mb PRAM by using ring type contact scheme. This advanced ring type BEC scheme was prepared by depositing very thin TiN films inside a contact hole, and then core dielectrics was uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce a reset current with low set resistance, and also maintain a uniform cell distribution. Thus, it is clearly demonstrated that the ring type BEC technology can exhibit strong feasibility of high density 256 Mb PRAM and beyond.
[Show abstract][Hide abstract] ABSTRACT: Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10μm CMOS technology.
[Show abstract][Hide abstract] ABSTRACT: Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.
[Show abstract][Hide abstract] ABSTRACT: We investigate the key factors for scalable high density MRAM. Specifically we examine problems such as large switching field, small sensing margin and writing disturbance following a decrease in size. We demonstrate these problems and suggest several solutions for realizing high density MRAM.
[Show abstract][Hide abstract] ABSTRACT: Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.
[Show abstract][Hide abstract] ABSTRACT: A 64 Mb phase change random access memory, based on 0.18 μm technology is developed. We proposed several key factors such as BEC and GST cell size, contributing to stabilization of writing current for reversible cell transition. By reducing writing current to 1.1 mA through such optimization, we have developed a 64 Mb PRAM. With memory functions and reliability tests, the feasibility for developing high-density 64 Mb PRAM is presented.
[Show abstract][Hide abstract] ABSTRACT: We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18μm-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns.
[Show abstract][Hide abstract] ABSTRACT: PRAM is a promising memory that can solve the problems of conventional memory. Writing current reduction is the most important technical challenges in order to maximize the advantage of PRAM in scaling. We will present the high density 64Mb PRAM based on 0.18 μm CMOS technologies. And Various approaches to reduce the writing Current will be reviewed.
[Show abstract][Hide abstract] ABSTRACT: PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18μm CMOS technology.
[Show abstract][Hide abstract] ABSTRACT: By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.
[Show abstract][Hide abstract] ABSTRACT: We have developed a novel cell structure of PRAM with metal interlayer. This novel structure has been proposed to solve the over-programming fail. We have examined the cause of over-programming by simulation of the phase transition of chalcogenide and successfully demonstrated reliable cell operation of this novel structure in writing current level, crystallization speed, and endurance. It can be explained by a model in which the metal interlayer is a local heat sink and the top GST layer is a thermal insulator.
[Show abstract][Hide abstract] ABSTRACT: The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 μm design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.
[Show abstract][Hide abstract] ABSTRACT: We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 μm-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.
[Show abstract][Hide abstract] ABSTRACT: This paper introduces a novel surrounded gate STTM cell technology to improve retention and read disturb characteristics. In the memory cells previously reported, the device structures limits the CMOS-compatible memory integration and the operation voltage scaling of the memory cells. The proposed cell architecture overcomes this problem and also improves the read disturb characteristics. The proposed memory cell was fabricated using the 0.18 um design rule based on the low power SRAM process technology. This paper demonstrate an the device characteristics of the proposed memory cell and the improvement of tin a read disturb characteristics.
[Show abstract][Hide abstract] ABSTRACT: We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.
[Show abstract][Hide abstract] ABSTRACT: The Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.