R. Blumgold

Wright-Patterson Air Force Base, Dayton, Ohio, United States

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Publications (4)0 Total impact

  • Robert Blumgold · Nima Emami · Robert Gillen
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    ABSTRACT: A two stage Pipelined Delta Sigma Modulator ADC is presented for broad band, high resolution applications. The unique architecture incorporates a first order delta sigma modulator in each stage and combines the most significant bits of the first stage with the second stage output to produce 11-13 bit resolution. The input bandwidth is 62.5 MHz and the sampling frequency of 1 GHz results in an over sampling ratio of 8 for the first order modulators. MATLAB simulations for the two stage ADC show 13-15 bit resolution. A transistor level design in 0.18 um CMOS for the two stage ADC was captured and simulated with Cadence show 12 bit resolution with a 50 MHz input. The ADC was fabricated in 0.18 um CMOS technology on a 10 square millimeter die.
    No preview · Conference Paper · Sep 2006
  • S. Ren · R. Siferd · R. Blumgold · R. Ewing
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    ABSTRACT: A design procedure is presented for a hardware efficient FIR compensation filter as a component in a delta sigma modulator analog to digital converter using cascaded sine low pass filters. The combination of the sine low pass filters and the hardware efficient FIR compensation filter results in a 21% saving in hardware (chip area) compared to a single FIR low pass filter
    No preview · Conference Paper · Sep 2005
  • S. Ren · R. Siferd · R. Blumgold
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    ABSTRACT: Many system on chip (SOC) architectures are pushing the analog to digital interface into the RF/IF region. A critical component for such architectures is a band pass analog to digital converter (BPADC). A parallel time interleaved (PTI) delta sigma BPADC is presented which supports RF/IF center frequencies for SOC applications. Three low pass delta sigma modulators sampling at 1 GHz are time interleaved to obtain a BPADC with center frequencies of 1 or 2 GHz in 0.18μm CMOS technology. Resolution depends on bandwidth with 8 bits achievable for a 100 MHz bandwidth and 1 GHz sampling frequencies for the modulators. The BPADC center frequencies, resolution, and bandwidth can be modified by changing the sampling frequency of the modulators or the number of modulators that are time interleaved.
    No preview · Conference Paper · Oct 2004
  • Source
    C. Cerny · R. Blumgold · J. Cook · S. Bibyk · J. Fisher · R. Siferd · Si-Yu Ren
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    ABSTRACT: An important aspect in developing digital receivers is the reduction of analog components, which tend to be temperature sensitive and require calibration and result in a reduction in receiver accuracy. Digital receivers are a long-term goal of the Air Force, which strive for increased functionality interactive capability amongst air, space and ground based platforms. Therefore, in the proper designing of that digital receiver an intricate tradespace exists in order to maintain the power performance relationship needed to meet platform requirements, and reducing acquisition and lifecycle costs. This paper summarizes efforts to completely analyze two complementary enhancement-mode technologies, GaAs CHFET and SOI CMOS, which could be implemented at the front end of the digital receiver and result in an appropriate power/performance improvement. This effort begins with a detailed radio frequency (RF) characterization of each technology, the building of a complete RF model, and the correct choice of enhancement-mode, high performance mixed-signal circuit designs. This type of ground level approach is critical to any future digital receiver architecture where platform power budget constraints must be met, while producing the maximum performance
    Preview · Conference Paper · Feb 2000

Publication Stats

9 Citations

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Institutions

  • 2006
    • Wright-Patterson Air Force Base
      Dayton, Ohio, United States
  • 2004
    • Wright State University
      • Department of Electrical Engineering
      Dayton, OH, United States