Woopyo Jeong

Purdue University, West Lafayette, Indiana, United States

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Publications (12)11.53 Total impact

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    ABSTRACT: Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.
    Full-text · Article · Feb 2010 · Journal of Signal Processing Systems
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    Hiroaki Suzuki · Woopyo Jeong · Kaushik Roy
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    ABSTRACT: Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose low power adders that adaptively select supply voltages based on the input vector patterns. First, we apply the proposed scheme to the Ripple Carry Adder (RCA). A prototype design by a 0.18 μm CMOS technology shows that the Adaptive VDD 32-bit RCA achieves 25% power improvement over the conventional RCA with similar speed. The proposed adder cancels out the delay penalty, utilizing two innovative techniques: carry-skip techniques on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. As an expansion to faster adder architectures, we extend the proposal to the Carry-Select Adders (CSA) composed of the RCA sub-blocks. We achieved 24% power improvement on the 128-bit CSA prototype over a conventional design. The proposed scheme also achieves stand-by leakage power reduction—for 32-bit and 128-bit Adaptive RCA and CSA, respectively, 62% and 54% leakage reduction was possible.
    Preview · Article · Apr 2007 · IEICE Transactions on Electronics
  • Woopyo Jeong · Kaushik Roy
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    ABSTRACT: We present a dual transition preferentially sized (DTPS) logic that uses two separate paths - one for the fast propagation of low-to-high signal and the other for fast propagation of high-to-low signal. DTPS logic is suitable for multistage buffers and critical sections of datapaths requiring good noise immunity and low power dissipation while achieving high performance. We derived formulas to obtain optimal tapering factors of multistage buffers based on preferentially sized (PS) inverters, and implemented DTPS logic using the optimal tapering factors. We fabricated datapaths based on static CMOS logic, domino logic, and DTPS logic in 0.18-μm technology. DTPS logic shows 15% and 16% improvements in performance and power dissipation, respectively, over domino, and 42% improvement in performance compared to static CMOS.
    No preview · Article · Mar 2005 · IEEE Journal of Solid-State Circuits
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    ABSTRACT: The polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents an efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level. At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352 mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.
    Full-text · Conference Paper · Jun 2004
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    ABSTRACT: This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm<sup>2</sup> area.
    Full-text · Article · Mar 2004 · IEEE Journal of Solid-State Circuits
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    W. Jeong · B.C. Paul · Kaushik Roy
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    ABSTRACT: The increase in power consumption due to interconnects and the variation in delays (delay spread) among long interconnects are becoming important issues for design of high performance and low power circuits in scaled technologies. We propose an adaptive supply voltage technique for low swing interconnects. The proposed technique assigns different supply voltages to drive interconnects based on their delay. The voltage assignment is done only once during the initialization period of the circuit. Hence, there is no extra power consumption in the active mode. We also show that there is an optimum number of supply voltages required to achieve maximum power saving. Simulation results show that for a set of 64 buses we can achieve 42.8% and 55.9% reductions in the power consumption and delay spread, respectively.
    Preview · Conference Paper · Feb 2004
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    Hiroaki Suzuki · Woopyo Jeong · Kaushik Roy
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    ABSTRACT: Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.
    Preview · Conference Paper · Feb 2004
  • H. Suzuki · W. Jeong · Kaushik Roy
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    ABSTRACT: Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power adder, which adoptively selects supply voltages based on the input vector patterns. We prototyped a 32-bit Ripple Carry Adder and analyzed the power consumption and performance in details. Results show 29% improvement in power consumption over a conventional ripple carry adder with comparable performance.
    No preview · Conference Paper · Nov 2003
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    Woopyo Jeong · Kaushik Roy
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    ABSTRACT: This paper proposes Dual Transition Skewed Logic (DTSL) based Carry Select Adder (CSA) suitable for processing units requiring low power and high performance with high noise immunity. We implemented 31-bit Carry Select Adders in three different logic styles: Dual Transition Skewed Logic (DTSL), Domino, and conventional static CMOS in TSMC 0.25um technology and compared them in terms of performance, power consumption and layout area. CSA using DTSL shows 36.7% and 17.7% improvements in power dissipation and performance, respectively, over domino, and 40.4% improvement in performance compared to a static CMOS CSA.
    Preview · Conference Paper · Feb 2003
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    ABSTRACT: We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on the Wallace tree multiplier.
    Full-text · Conference Paper · Feb 2002
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    Woopyo Jeong · Kaushik Roy · Cheng-Kok Koh
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    ABSTRACT: In this paper, we present a low power and high performance Carry Select Adder (CSA) using Dual Transition Skewed Logic (DTSL) suitable for high noise immunity. We compared DTSL Carry Select Adder with domino and static CMOS adders with respect to performance, power consumption and area, using UMC 0.18um technology. The comparison shows the superior properties of the DTSL over domino and the static CMOS logic: 19% to 27% improvement in power dissipation over domino with similar performance is observed.
    Preview · Article · Dec 2001
  • Woopyo Jeong · K. Roy · Cheng-Kok Koh
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    ABSTRACT: In this paper, we present a low power and high performance Carry Select Adder (CSA) using Dual Transition Skewed Logic (DTSL) suitable for high noise immunity. We compared DTSL Carry Select Adder with domino and static CMOS adders with respect to performance, power consumption and area, using UMC 0.18µm technology. The comparison shows the superior properties of the DTSL over domino and the static CMOS logic: 19% to 27% improvement in power dissipation over domino with similar performance is observed.
    No preview · Conference Paper · Oct 2001