Publications (2)0 Total impact
Conference Paper: Integration challenges of 0.1 μm CMOS Cu/low-k interconnects[Show abstract] [Hide abstract]
ABSTRACT: The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 μm CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.
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ABSTRACT: In this work components of the next generation 0.10 μm CMOS technology are presented. They form the core of a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 Å gate oxide (24 Å inversion Tox) while low power devices use 25 Å gate oxide (31 Å inversion Tox) for reduced gate leakage. Gate lengths range from 65 nm for the high performance devices to 90 nm for the low power devices. Both 3.3 V and 2.5 V I/Os are supported using 70 Å and 50 Å oxide devices. The backend employs low-k (k~3) dielectric with multiple levels of Cu metallization. The high density 6T SRAM cell size is 1.33 μm<sup>2 </sup>
IBMArmonk, New York, United States