Publications (17)10.53 Total impact

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    [Show abstract] [Hide abstract] ABSTRACT: We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, f<sub>T</sub>, of 305 GHz and 256 GHz, respectively, at 0.5V V<sub>DS</sub>, suitable for high speed, very low power logic applications. The InSb transistors demonstrate 50% higher unity gain cutoff frequency, f<sub>T</sub>, than silicon NMOS transistors while consuming 10 times less active power
    Full-text · Conference Paper · Jan 2006
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    [Show abstract] [Hide abstract] ABSTRACT: We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with I<sub>DSAT</sub>=1.4 mA/mum and 1.1 mA/mum respectively (I<sub>OFF</sub>=100nA/mum, V<sub>CC </sub>=1.1V and L<sub>G</sub>=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade I<sub>ON</sub>-I<sub>OFF</sub> and DeltaS
    Full-text · Conference Paper · Jan 2006
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    [Show abstract] [Hide abstract] ABSTRACT: High-κ gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging non-silicon nanoelectronic transistors. In addition, high-κ gate dielectrics and metal gates are required for the successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high ION/IOFF ratios.
    Full-text · Article · Jun 2005 · Microelectronic Engineering
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    [Show abstract] [Hide abstract] ABSTRACT: Several key emerging nanoelectronic devices, such as Si nanowire field-effect transistors (FETs), carbon nanotube FETs, and III-V compound semiconductor quantum-well FETs, are assessed for their potential in future high-performance, low-power computation applications. Furthermore, these devices are benchmarked against state-of-the-art Si CMOS technologies. The two fundamental transistor benchmarking metrics utilized in this study are: (i) CVII versus L<sub>G</sub>; and ii) CVII versus I<sub>ON</sub>/I<sub>OFF</sub>. While intrinsic device speed is emphasized in the first metric, the tradeoff between device speed and off-state leakage is assessed in the latter. For high-performance and low-power logic applications, low CVII and high I<sub>ON</sub>/I<sub>OFF</sub> values are both required. Based on the results obtained, the opportunities and challenges for these emerging novel devices in future logic applications are highlighted and discussed.
    Full-text · Conference Paper · May 2005
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    [Show abstract] [Hide abstract] ABSTRACT: Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L<sub>g</sub>; 2) energy-delay product versus L<sub>g</sub>; 3) subthreshold slope versus L<sub>g</sub>; and 4) CV/I versus on-to-off-state current ratio I<sub>ON</sub>/I<sub>OFF</sub>. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.
    Full-text · Article · Apr 2005 · IEEE Transactions on Nanotechnology
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    [Show abstract] [Hide abstract] ABSTRACT: Sustaining Moore's Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore's Law will continue at least through early next decade. By combining silicon innovations with other nanotechnologies on the same Si platform, it is expected that Moore's Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotubefield-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.
    Full-text · Conference Paper · Nov 2004
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    [Show abstract] [Hide abstract] ABSTRACT: Sustaining Moore's Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.
    Full-text · Conference Paper · Oct 2004
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    [Show abstract] [Hide abstract] ABSTRACT: We show experimental evidence of surface phonon scattering in the high-κ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-κ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO<sub>2</sub>/poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-κ/metal-gate CMOS transistors with desirable threshold voltages.
    Preview · Article · Jul 2004 · IEEE Electron Device Letters
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    [Show abstract] [Hide abstract] ABSTRACT: We integrate a strained Si channel with HfO<sub>2</sub> dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO<sub>2</sub>, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO<sub>2</sub>/strained Si interface, we measure mobility at various temperatures and extract the various scattering components.
    Full-text · Conference Paper · Jan 2004
  • [Show abstract] [Hide abstract] ABSTRACT: We report on the materials development, device fabrication and characterization of biaxial compressively strained SiGe surface channel pMOS transistors with high-k dielectric and metal gate electrode. The compressively strained SiGe (Ge = 25-30%) surface channel pMOS transistors exhibit hole mobility significantly better than the universal mobility curve for SiO2 with inversion electrical oxide thickness of 1.45nm (EOT =1 nm). No reduction in strain-induced hole mobility enhancement is observed at high vertical electric field in the channel for this approach.
    No preview · Article · Jan 2004
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    [Show abstract] [Hide abstract] ABSTRACT: We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.
    Preview · Conference Paper · Dec 2003
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    [Show abstract] [Hide abstract] ABSTRACT: In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.
    Preview · Conference Paper · Jul 2003
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    [Show abstract] [Hide abstract] ABSTRACT: Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.
    Full-text · Conference Paper · Jul 2003
  • [Show abstract] [Hide abstract] ABSTRACT: Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.
    No preview · Article · Jul 2003 · Physica E Low-dimensional Systems and Nanostructures
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    [Show abstract] [Hide abstract] ABSTRACT: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.
    Full-text · Article · May 2003 · IEEE Electron Device Letters
  • [Show abstract] [Hide abstract] ABSTRACT: This paper reports, for the first time, the high-frequency response of NMOS and PMOS transistors in an integrated CMOS technology with 100 nm physical gate length and alternative gate dielectrics such as ZrO<sub>2</sub> and HfO<sub>2</sub> with TiN/PolySi gate electrode. It is shown that the dielectric constants of ZrO<sub>2</sub>, HfO<sub>2 </sub> and SiO<sub>2</sub> are invariant with respect to operating frequency at least up to 20 GHz. In addition, the cutoff frequency f<sub>t</sub> of the 100 nm CMOS transistor test structures with ZrO<sub>2</sub> gate dielectric was measured to be equal to 46 GHz for NMOS and 47 GHz for PMOS. The corresponding f<sub>t</sub> values for HfO <sub>2</sub> were 45 GHz for NMOS and 35 GHz for PMOS. High-K film transistors with 80 nm physical gate lengths, 7 μm gate width and layout optimized for high frequency testing were also fabricated. The NMOS devices achieved an f<sub>t</sub> of 83 GHz and an f<sub>max</sub> of 35 GHz, while the PMOS yielded 41 GHz and 25 GHz respectively. These results are very similar to those of CMOS transistors with SiO<sub>2 </sub> gate dielectric at similar physical gate lengths and widths. These results are very encouraging and suggest that high-K gate dielectrics can be used for high-frequency logic applications
    No preview · Conference Paper · Feb 2001
  • [Show abstract] [Hide abstract] ABSTRACT: In this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates significant performance gain over bulk Si transistors without the floating body effect (FBE). We have fabricated depleted-substrate CMOS transistors on thin silicon body (&les;30 nm) with physical gate lengths down to 50 nm which show much steeper subthreshold slopes (&les;75 mV/decade) and improved DIBL (&les;50 mV/V) over both partially-depleted (P-D) SOI and bulk Si, for both PMOS and NMOS transistors. The salicide formation and high parasitic resistance problems associated with the use of thin Si body can be overcome by using raised source/drain. Depleted-substrate PMOS transistors with 50 nm physical gate length and raised source/drain were fabricated and achieved I<sub>on</sub>=0.65 mA/um and I<sub>off</sub>=9 nA/um at V<sub>cc</sub>=1.3 V. This PMOS drive current is the highest ever reported, and is about 30% higher than any previously published PMOS I <sub>on</sub> value for both PD-SOI and bulk Si at a given I<sub>off </sub>. The use of raised source/drain improved the I<sub>on</sub> of the depleted-substrate NMOS transistors by ~20%. Depleted-substrate NMOS transistors with 65 nm physical gate length and raised source/drain achieved DIBL=45 mV/V, subthreshold slope=75 mV/decade, I<sub>on</sub>=1.18 mA/um and I<sub>off</sub> =60 nA/um at V<sub>cc</sub>=1.3 V, as well as significant improvement in Id-Vd characteristics due to a 60% reduction in DIBL and >25% improvement in subthreshold slope over the bulk Si
    No preview · Conference Paper · Feb 2001