Zsolt Tokei

imec Belgium, Louvain, Flanders, Belgium

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Publications (111)56.63 Total impact

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    ABSTRACT: In this work, we evaluate the material properties of graphene and assess the potential application of graphene to replace copper wires in Back-End-Of-Line (BEOL) interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we evaluate single and multi-layer graphene wires and we measure carrier mean free paths (MFP) above ~ 110 nm. However, contact engineering will be the key issue for integration of graphene as interconnect.
    No preview · Article · Jan 2016 · Microelectronic Engineering
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    ABSTRACT: Achieving low resistance contacts to graphene is a common concern for graphene device performance and hybrid graphene/metal interconnects. In this work, we have used the circular Transfer Length Method (cTLM) to electrically characterize Ag, Au, Ni, Ti, and Pd as contact metals to graphene. The consistency of the obtained results was verified with the characterization of up to 72 cTLM structures per metal. Within our study, the noble metals Au, Ag and Pd, which form a weaker bond with graphene, are shown to result in lower contact resistance (Rc) values compared to the more reactive Ni and Ti. X-ray Photo Electron Spectroscopy and Transmission Electron Microscopy characterization for the latter have shown the formation of Ti and Ni carbides. Graphene/Pd contacts show a distinct intermediate behavior. The weak carbide formation signature and the low Rc values measured agree with theoretical predictions of an intermediate state of weak chemisorption of Pd on graphene.
    No preview · Article · Oct 2015 · Applied Physics Letters
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    ABSTRACT: For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- $V_{rm th}$ optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.
    Full-text · Article · Oct 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm 1/2 pitch Meander-Fork structure, leading to keff below 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.
    Full-text · Article · Aug 2015 · Applied Physics Letters
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    ABSTRACT: This paper analyzes the impact of the interconnect variation at the system level in terms of clock frequency based on a fast and efficient system-level variation-aware design methodology. Various types of interconnect variations are compared, such as the critical dimension for line/core and spacer, etch, chemical mechanical polishing (CMP), and overlay variations. The 3σ values for these independent variation values are extracted from various fabrication processes, including the litho-etch-litho-etch (LELE) double patterning, self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP). The results indicate that the impact of the interconnect variation on the clock frequency increases for a processor at a smaller technology node, especially for the CMP variation. For the impact of the combination of five sources of interconnect variations, the processor using the SADP performs the best. The overlay variation and the spacer variation have a larger impact on the LELE double patterning and the SAQP patterning techniques. Up to 8% and 16% of the frequency drops are observed based on 1x and 2x of the default 3σ values, respectively.
    Full-text · Article · Jul 2015 · IEEE Transactions on Electron Devices
  • K. Croes · D. Kocaay · I. Ciofi · J. Bömmels · Z. Tokei
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    ABSTRACT: We investigate the impact of process variability on BEOL TDDB lifetime model assessment. The change in functional form of TDDB lifetime plots due to line-to-line variability and line-edge-roughness has been quantified in the field range in which long term TDDB measurements have been obtained. We found that the Pearson R2, which is used as a measure of linearity of a lifetime plot, did not significantly change due to process variability. Where process variability has a significant effect on TDDB and needs to be taken into account during data analysis, our simulations suggest that it does not have an impact on BEOL TDDB lifetime model assessment. We propose that the conclusions from recent literature reports which point in the direction of a less conservative model compared to the √E-model are valid, although they do not take process variability into account during the data analysis.
    No preview · Article · May 2015
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    ABSTRACT: The intrinsic Time Dependent Dielectric Breakdown properties of the spacer between gate and first level local interconnects are assessed for dielectrics and spacings compatible with N7 and beyond. The intrinsic reliability properties down to 3nm thickness of standard LPCVD Si3N4- and PECVD Si3N4-films as well as more advanced Al2O3- and low-k CVD SiN-layers have been studied using imec's pcap test vehicle. It turned out that the leakage current of the more advanced films are not worse compared to the more standard layers. Besides, their reliability performance, in terms of Emax, is the same or even slightly better. Down to 3nm thickness, Emax-values higher than 3.5MV/cm were obtained for all dielectrics studied. Fundamental insight in the breakdown processes is obtained by testing a wide thickness range (3-20nm) for the PECVD Si3N4-layer, where higher Emax and QBD were found for the thinner layers, suggesting that less damage is created by electrons when injecting them into thinner films (fluence driven failure mechanism). A difference in leakage and reliability when applying different polarities suggests different mechanisms playing a role when the electrons are injected from the interconnect or from the gate metal. Finally, field simulations at critical locations in the studied structure were used to assess places of higher local field enhancement. We found that at these places, the fields were still lower compared to the Emax-values of the intrinsic films, suggesting that scalability down to 3nm spacer thickness is intrinsically reliable.
    Full-text · Article · May 2015
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    ABSTRACT: For characterizing the electromigration (EM) reliability of advanced interconnects, we propose a constant voltage approach (CV-EM) as an alternative method to traditional constant current tests (CI-EM). As extremely scaled interconnects require very thin barriers, their current shunting capabilities will be reduced. When close to full void formation, we show that this lack of current shunting capability leads to unrealistically high stress conditions during CI-EM while more realistic stresses are induced during CV-EM. We also demonstrate that the void detection capability is highly improved after CV-EM. We use simulations and experiments to compare CV-EM with CI-EM where we obtain a) slightly longer lifetimes for CV-EM, b) the same failure mechanisms and c) similar Ea and n values.
    No preview · Article · May 2015
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    ABSTRACT: Based on realistic circuit- and system-level simulations, graphene interconnects are analyzed in terms of multiple material properties, such as the mean free path (MFP), the contact resistance, and the edge roughness. The benchmarking results indicate that the advantage of using graphene interconnects occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay product (EDP). At the circuit level, one representative circuit, a 32-bit adder, is investigated, where up to 40% and 70% improvements in delay and EDP are observed. At the system-level analysis, an ARM Cortex-M0 processor is synthesized, and placement and routing are performed. After replacing copper interconnects with multilayer graphene interconnects, up to 15% and 22% performance improvements in clock frequency and EDP have been observed. It is also demonstrated that the benefits of using graphene for the ARM core processor are strongly dependent on the quality of the graphene, such as the MFP and the edge roughness.
    Full-text · Article · May 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: The introduction of Multiple Patterning (MP) in sub-32nm technology nodes may pose severe variability problems in wire resistance and capacitance of IC circuits. In this paper we evaluate the impact of this variability on the performance of SRAM cell arrays based on the 10nm technology node, for a relevant range of process variation assumptions. The MP options we consider are the triple Litho-Etch (LE3) and the Self Aligned Double Patterning (SADP), together with Single Patterning Extreme-UV (EUV). In addition to the analysis of the worst-case variability scenario and the impact on SRAM performance, we propose an analytical formula for the estimation of SRAM read time penalty, using the RC variation of the bit line and the array size as input parameters. This formula, verified with SPICE simulations, allows a fast extraction of the statistical distribution of the read time penalty, using the Monte-Carlo method. Results on each patterning option are presented and compared.
    No preview · Conference Paper · Mar 2015
  • Kristof Moors · Bart Soree · Zsolt Tokei · Wim Magnus
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    ABSTRACT: We calculate the resistivity contribution of tilted grain boundaries with varying parameters in sub-10nm diameter metallic nanowires. The results have been obtained with the Boltzmann transport equation and Fermi's golden rule, retrieving correct state-dependent relaxation times. The standard approximation schemes for the relaxation times are shown to fail when grain boundary tilt is considered. Grain boundaries tilted under the same angle or randomly tilted induce a resistivity decrease.
    Preview · Conference Paper · Jan 2015
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    ABSTRACT: In recent year, two innovative strategies have been proposed to decrease plasma-induced low-k damage: the P4 approach [Frot et al., 2011] and the cryogenic etch approach [Zhang et al., 2013]. The P4 or “pore stuffing” uses an extrinsic sacrificial pore filler, allowing protection during plasma etching and metallization steps. The cryogenic etch is based on in-situ pore filling by etch byproducts and/or SiOFx sidewall passivation. In this work, a PMO spin-on material with pristine k = 2.31 from SBA has been integrated on 300mm wafers. The integration vehicle uses narrow-spacing structures, i.e. 30nm low-k lines at 180nm pitch. For the cryogenic etch approach, after lithography, the SiC/SOC/SOG hardmask is trimmed and opened using standard etch. Low-k etching is performed by means of a SF6-based plasma chemistry in an ICP chamber equipped with a liquid-N2 cooled substrate holder set at a base temperature of -120°C. Careful optimization of etch conditions allows to considerably decrease the loss of Si-CH3 bonds, keeping an acceptable etch rate, good hardmask selectivity, and reduced bottom roughness. After patterning and subsequent byproduct removal by annealing, a conventional Cu metallization is performed using TaNTa barrier, Cu seed and electroplating. After chemical-mechanical polishing (CMP) and SiC passivation, functional circuits gave integrated dielectric constant of kint = 2.38, i.e. showing a Δk = 0.07 relative to pristine. For the pore stuffing approach, PMMA was used as filling material and driven in after low-k deposition. Due to thermal instability of PMMA, a low-temperature Si3N4 hardmask was used, as well as low-temperature TaNTa barrier. PMMA was removed after CMP, by means of He-H2 downstream plasma ashing or thermal decomposition. Functional circuits gave integrated dielectric constants kint = 2.73 (thermal unstuffing) and kint = 3.14 (He-H2 ashing). By comparison of both approaches, it is observed that pore stuffing increases interconnect flow complexity, by the addition of stuffing and unstuffing steps which can also damage the low-k material; however post-etch surfaces are smooth and barrier metal penetration is suppressed. The pore stuffing approach could be improved by using more thermally stable polymers and the search for damage-free unstuffing methods. The current cryogenic etch process requires only minor changes into the process flow, however currently it requires a base temperature of -120°C. The cryogenic etch process could be improved by the use of plasma additives enhancing by-products condensation and/or pre-condensation steps. We acknowledge support from the European Union under grant agreement No. 318804 (SNM).
    No preview · Conference Paper · Nov 2014
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    ABSTRACT: Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.
    No preview · Conference Paper · Sep 2014
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    ABSTRACT: This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.
    No preview · Conference Paper · Sep 2014
  • Kristof Moors · Bart Soree · Zsolt Tokei · Wim Magnus
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    ABSTRACT: We study the resistivity scaling in nanometer-sized metallic wires due to surface roughness and grain-boundaries, currently the main cause of electron scattering in nanoscaled interconnects. The resistivity has been obtained with the Boltzmann transport equation, adopting the relaxation time approximation of the distribution function and the effective mass approximation for the conducting electrons. The relaxation times are calculated exactly, using Fermi's golden rule, resulting in a correct relaxation time for every sub-band state contributing to the transport. In general, the relaxation time strongly depends on the sub-band state, something that remained unclear with the methods of previous work. The resistivity scaling is obtained for different roughness and grain-boundary properties, showing large differences in scaling behavior and relaxation times. Our model clearly indicates that the resistivity is dominated by grain-boundary scattering, easily surpassing the surface roughness contribution by a factor of 10.
    Preview · Article · Aug 2014 · Journal of Applied Physics
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    ABSTRACT: The semiconductor industry returned growth and reached record revenues in 2013, breaking $300 billion for the first time after the industry had contracted in 2011 and 2012. A study released by AlixPartners looked at a broader picture of the semiconductor value chain, including areas such as equipment suppliers and packaging and test companies. The research showed that outside of the top 5 companies, the remainder of the 186 companies surveyed had declining earnings before interest, taxes, depreciation, and amortization. Semico Research has estimated that the total cost of an SoC development, design, intellectual property (IP) procurement, software, testing has tripled from 40/45 nanometers to 20 nm and could exceed $250 million for future 10-nm designs. By 10 nm, end markets would have to result in more than $2.5 billion to recoup projected development costs. The Internet of Things alone will result in a tremendous amount of new semiconductor innovation that in turn will likely lead to volume markets.
    No preview · Article · Jul 2014 · Solid State Technology
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    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
    No preview · Article · Jun 2014 · Microelectronics Reliability
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    ABSTRACT: Different advanced patterning schemes have been compared with respect to the effect of line-overlay and via-misalignment on dielectric reliability, where the effects on the Weibull slope, on the TDDB lifetime and on Vmax were studied. The patterning schemes compared in this study are litho-etch-litho-etch and self-aligned-double-patterning. For typical intrinsic reliability parameters, in comparison with the ideal case of 0nm line-overlay and via-misalignment, the self-aligned-double-patterning scheme with a 3σ via-misalignment of 6nm leads to a Vmax reduction of 26%. The additional line-overlay errors that must be taken into account for the litho-etch-litho-etch patterning scheme leads to a reduction of Vmax by 43%.
    No preview · Conference Paper · Jun 2014
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    ABSTRACT: Different approaches combining Finite Element Simulations and in-situ electrical measurement of stress sensors during a BABSI test are proven to be ideal combination to quantitatively compare the strength of BEOL layers. It is shown that detectable mechanical failures during a shear or BABSI test are insufficient to detect early opens of the metal interconnections. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the Cu pillar and finite element simulations. Next, the risk of cohesive and adhesive failures in the Cu/low-k layers is evaluated in function of stiffness of low-k and design of metal interconnections.
    No preview · Conference Paper · Jun 2014
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    ABSTRACT: Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
    No preview · Conference Paper · Jun 2014

Publication Stats

595 Citations
56.63 Total Impact Points

Institutions

  • 2001-2016
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 2009
    • Newcastle University
      • School of Electrical and Electronic Engineering
      Newcastle upon Tyne, ENG, United Kingdom