[Show description][Hide description] DESCRIPTION: In this article, a 3.2 Gb/s serial link transceiver,
that can be implemented in 0.35 lm CMOS technology is
presented. In this transceiver a new multi-level pulsewidth-
amplitude modulation technique is used. The symbol
rate is reduced, while the minimum pulse width (PW) is
increased considerably, using the proposed modulation.
The PW is larger than the conventional NRZ data format,
with PW of Tb, so the ISI will be improved. The multiphase
output of a three stage ring oscillator VCO in the
PLL is used to modulate and to demodulate the signal. A
new charge pump circuit is also introduced to decrease the
mismatch between up and down paths. The peak to peak
jitter of recovered clock is 21 ps at 800 MHz. The recovered
data has the peak to peak jitter of 51 ps. The transmitter
and receiver power consumption is 220 and 35 mW,
[Show abstract][Hide abstract] ABSTRACT: An open loop high speed CMOS differential source follower buffer with improved linearity and negligible extra power consumption in comparison to conventional one is presented. The conventional linear buffers which are commonly implemented in closed loop structure limits the maximum achievable frequency. On the other hand, linearity of differential open loop buffers (source followers) is restricted due to the third harmonic distortion. The proposed differential source follower buffer improves linearity by directly neutralizing third harmonic distortion. Also, a strict analysis on the third harmonic distortion is organized which confirms considerable linearity improvement. The new buffer achieves 86 dB linearity for a 100 MHz 1.6 Vp–p output amplitude, with 2 pF load capacitor at each side in other wise 77 dB linearity of conventional buffer, 95 dB linearity for a 100 MHz 1.0 Vp–p output amplitude in other wise 85 dB linearity of conventional one and 84 dB linearity at dual-tone input frequency in other wise 74.7 dB linearity of conventional one. The power consumption of the proposed buffer is 48 mw while the conventional buffer consumes 42 mw which means about 14 % increases in power consumption leads to 10 dB linearity improvement. The buffer is implemented by using 0.35 μm dual-poly quadruple metal CMOS technology.
No preview · Article · Oct 2015 · Analog Integrated Circuits and Signal Processing
[Show abstract][Hide abstract] ABSTRACT: Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard FLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3 V power supply.
No preview · Article · Aug 2015 · Journal of Intelligent and Fuzzy Systems
[Show abstract][Hide abstract] ABSTRACT: This paper, presents a CMOS design of a novel current-mode analog multiplier/divider which can be used in defuzzifier block for fuzzy logic controllers (FLC) and neuro-fuzzy systems to realize the centroid strategy. This analog multiplier/divider circuit operates based on the square-law characteristic of a MOS transistor operated in the saturation region. The proposed circuits are designed in 0.18μm CMOS technology with a power supply of 2 Volt. The maximum delay for the proposed circuit is 50.7ns that restricts the inference speed of the total fuzzy logic controller to 20 MFLIPS in its turn. The maximum power consumption of this circuit is about 626μW and can be implemented in 84μm×36μm. The functionality of the proposed multiplier/divider in the defuzzifier block of a typical (3×3) FLC was evaluated and results indicate that the percentage of root mean squarer error (RMSE) of the output surface is 1.08 of the full scale output. To obtain the ideal output surface MATLAB software has been utilized.
No preview · Article · Aug 2015 · Journal of Intelligent and Fuzzy Systems
[Show abstract][Hide abstract] ABSTRACT: In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in 0.18 μm process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.
[Show abstract][Hide abstract] ABSTRACT: In this paper a novel structure is presented as a voltage comparator, and a reliable offset cancellation technique is utilized as well. Moreover a comprehensive post layout simulation method is described to evaluate a vast verity of comparators in order to find out whether the designed structure will operate properly in the post fabrication (solid state) tests or not. A single stage architecture with a simple readout circuit leads to a low-offset low-power high-speed high-resolution comparator which qualifies for VLSI applications such as image sensors. Applying the reliable offset cancellation technique makes it qualified for high performance applications like high-speed high-resolution ADCs. The proposed comparator is simulated through the mentioned method in 0.18 µm standard CMOS technology, and 0.5 mV of accuracy in 1 G sample per second is obtained with a power consumption of 110 µW (150 µW with offset cancellation circuit) where an introduced offset of about 10 mV is cancelled to lower than 220 µV as well.
No preview · Article · Jul 2015 · Analog Integrated Circuits and Signal Processing
[Show abstract][Hide abstract] ABSTRACT: In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high-speed pipelined analogue-digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non-linearity error and 1.2 Vp-p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal-oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm2 of die area. Simulations are performed in HSPICE using level 49 models.
No preview · Article · Jul 2015 · IET Circuits Devices & Systems
[Show abstract][Hide abstract] ABSTRACT: A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6-4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, Simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.
No preview · Article · May 2015 · Journal of Circuits System and Computers
[Show abstract][Hide abstract] ABSTRACT: This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 mu W from a 1.8 V power supply using TSMC 0.18-mu m CMOS technology.
No preview · Article · Apr 2015 · Journal of Circuits System and Computers
[Show abstract][Hide abstract] ABSTRACT: The paper describes a novel PWM scheme called inverted-sine PWM (ISPWM) which uses a sinusoidal reference and an inverted-sine carrier. The ISPWM, when applied to a rectifier, has a better harmonic elimination and a higher average output voltage compared to a sine PWM (SPWM). The harmonic content of the ISPWM output for different values of the modulation index is computed and compared with that of a SPWM. The complete circuit for generating the ISPWM control signal for single and three phase ac-dc converters is developed. Experimental waveforms of voltages and currents are presented.
No preview · Article · Mar 2015 · IETE Journal of Research
[Show abstract][Hide abstract] ABSTRACT: This paper presents design of a digital fuzzy logic controller IC based on Active-rule-driven architecture. Different ideas have been used in inference and defuzzification stages to obtain high processing speed. This produces a parallel processing mechanism from fuzzification to defuzzification. The controller was designed by 0.35 μm CMOS technology and the layout design was obtained by MAGIC software which has 892274 μm2 size. The circuits were simulated using HSPICE software. The resulting speed for processing was 50 MHz (25 MFLIPS).
No preview · Article · Mar 2015 · IETE Journal of Research
[Show abstract][Hide abstract] ABSTRACT: The development of a PC-based fuzzy controller for controlling the speed of a dc motor is considered. It is shown that the proposed controller results in a reduced chattering around the set point as compared to a basic fuzzy controller. The performance of the fuzzy controller and its capability of optimizing the parameters like maximum overshoot and rise time are described. The results obtained on a practical dc motor control system are presented.
No preview · Article · Mar 2015 · IETE Journal of Research
[Show abstract][Hide abstract] ABSTRACT: An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.
No preview · Article · Feb 2015 · Journal of Circuits System and Computers
[Show abstract][Hide abstract] ABSTRACT: A novel topology for a high gain two-stage amplifier is proposed. The
proposed circuit is designed in a way that the non-dominant pole is at output
of the first stage. A positive capacitive feedback (PCF) around the second
stage introduces a left half plane (LHP) zero which cancels the phase shift
introduced by the non-dominant pole, considerably. The dominant pole is at the
output node which means that increasing the load capacitance has minimal effect
on stability. Moreover, a simple and effective method is proposed to enhance
slew rate. Simulation shows that slew rate is improved by a factor of 2.44
using the proposed method. The proposed amplifier is designed in a 0.18um CMOS
process. It consumes 0.86mW power from a 1.8V power supply and occupies
3038.5um2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9
MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR+ are
127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency,
which are relatively high and are other important properties of the proposed
amplifier. Moreover, Simulations show convenient performance of the circuit in
process corners and also presence of mismatch.
Full-text · Article · Nov 2014 · IET Circuits Devices & Systems
[Show abstract][Hide abstract] ABSTRACT: In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a −3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW.
No preview · Article · Oct 2014 · AEU - International Journal of Electronics and Communications
[Show abstract][Hide abstract] ABSTRACT: In this paper, a 16-phases 20MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35μm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3Volts supply voltage is subject to 75mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small active area, around 380μm×210μm including the clock generation circuit, which is proper to be repeatedly used inside the chip.
[Show abstract][Hide abstract] ABSTRACT: In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 A mu m standard CMOS technology with +/- A 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of +/- 10 mu A demonstrate a -3 dB bandwidth of 24.5 MHz, 475 mu W as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.
No preview · Article · Jul 2014 · Analog Integrated Circuits and Signal Processing
[Show abstract][Hide abstract] ABSTRACT: This article is attributed to a novel 4-2 compressor based on a new structure with a special feature of having no glitch at the output waveform. Speed enhancement is achieved through the quick production of Cout and optimum tuning of the width of utilizing transistors. The delay of the proposed structure is about 130ps in which the authenticity of our claim is proved by using the results extracted by Hspice software using CSMC 0.18μm technology.
[Show abstract][Hide abstract] ABSTRACT: What is discussed in this article is a current mode membership function generator (MFG) which consists of digital and analog parts or in other words it is a mixed mode MFG. The proposed MFG which consumes less power and perform in high speed can generate output shapes(S, Z, triangular and trapezoidal) and by exploiting 7 switches, slope and height altering and also horizontal shifting is available. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology.
[Show abstract][Hide abstract] ABSTRACT: This article discusses about a fuzzy controller. The fuzzifier is designed with a novel structure which is more suitable than other topologies and it has a high accuracy and speed. The processing unit, inference engine, is extracted out of reference  that is able to generate both maximum and minimum of its inputs currents simultaneously. Ultimately, the defuzzifier is simple and the center of area (COA) is used in this section. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology. The inference speed of this controller (with two inputs, one output and sixteen rules) is about 42.6 MFLIPS.