S. Barraud

University of Grenoble, Grenoble, Rhône-Alpes, France

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Publications (149)204.72 Total impact

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    ABSTRACT: The operation of hybrid circuits consisting of a single hole transistor coupled to a metal oxide semiconductor field effect transistor (MOSFET) is demonstrated at 350 K. The devices are designed at ultimate scaling with complementary metal oxide semiconductor technology on 300 mm diameter silicon on insulator wafers using deep ultra-violet lithography. Coulomb blockade oscillations up to 350 K are measured from silicon nanowire transistors with 20 nm Ω-gate length and diameter under 5 nm. These oscillations are exploited to produce inverter/amplifier, literal gate, negative differential resistance and memory loop circuits for multivalued (MV) logic and MV memory applications, via hybridization with MOSFET in SETMOS configuration. The fabrication and the operation of these SHT-MOSFET hybrid circuits at high temperature should spur single charge transistor integration into circuits for innovative applications in nanoelectronics.
    No preview · Article · Feb 2016
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    ABSTRACT: Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically-driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred MHz.
    Preview · Article · Nov 2015 · Nano Letters
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    ABSTRACT: This paper presents the fabrication and characterization of Ω-gate P-FET nanowires (NW) with a hybrid channel integration (Si and strained–SiGe (cSiGe) material). The compressive SiGe channels result from local Ge enrichment. We show that the hole effective mobility in cSiGe channels can be enhanced by 130% with respect to un-strained Si channel NWs. Effectiveness of cSGOI (Ge content=30%) channels with Si0.7Ge0.3:B raised sources/drains is demonstrated for ultra-scaled P-FET NWs (LG=14nm and Wtop=10nm) with an outstanding ION current (ION=1020µA/µm at IOFF<100nA/µm; VDS=VGS=-0.9V) and a good electrostatics control (DIBL<50mV/V).
    Full-text · Conference Paper · Nov 2015
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    ABSTRACT: In this paper, we investigate Bias Temperature Instabilities (BTI) in Ωfet nanowires exhibiting a very low interface states density ∼1010 cm2. Positive BTI is independent of the transistor width W and meets the 10 year lifetime requirements. On the other hand, Negative BTI is enhanced in narrow devices. To explain this effect, several scenarios are discussed by means of dedicated measurements i.e. charge pumping, BTI variability and 3D simulations. We first show that the oxide field in this 3D architecture cannot be responsible for this NBTI enhancement. Moreover we demonstrate by correlating NBTI variability and charge pumping measurements, that, the width dependence of NBTI may be explained by a stronger degradation of the interfacial oxide on the sidewall of the nanowire compared to the top interface.
    Full-text · Article · Nov 2015 · Microelectronic Engineering
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    ABSTRACT: We report the fabrication and the characterization of tunnel FETs fabricated on SiGe-On-Insulator with a High-κ Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on ID(VG) characteristics is presented and analyzed: compressive Si0.75Ge0.25 enables to increase by a factor of 25 the saturation currents, even at small gate length (LG = 50 nm). This large gain is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels).
    No preview · Article · Nov 2015 · Solid-State Electronics
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    ABSTRACT: We investigate Single-Event Transients (SET) in different designs of multiple-gate devices made of FinFETs with various geometries. Heavy ion experimental results are explained by using a thorough charge collection analysis of fast transients measured on dedicated test structures. Multi-level simulations are performed to get new insights into the charge collection mechanisms in multiple-gate devices. Implications for multiple-gate device design hardening are finally discussed.
    No preview · Article · Sep 2015 · Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms
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    Full-text · Article · Jul 2015 · Physical Review X
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    ABSTRACT: Radio-fRequency Reflectom-etry (RfR) is a technique that was developed to characterize the properties of transmission lines by observing reflected waveforms. today, it is widely used in a variety of applications, ranging from the detection of faulty wires in cables [1] and objects buried in the ground [2] to soil moisture detectors [3] and the measurement of dielectric properties of blood [4]. Recently, one important application of this technique, which requires a very small amount of applied power, was developed for the characterization of electronic nanostructures [5]. in this implementation , a microwave radio-frequency (Rf) signal is sent to a resonator coupled to the specimen to be studied. if in a specimen the change of some external parameter (e.g., gate voltage) leads to a change of an active [figure 1(a)] or a reactive (typically, capacitive) load [ figure 1(b)] to the resonator, the self-resonance is affected, resulting in a change of magnitude [figure 2(a)] and phase [figure 2(b)] of the reflected signal. if an impedance matching condition is achieved, the modification of the specimen parameter (e.g., the increase of its resistance) will lead to a very significant change in the reflection coefficient C [figure 2(a)]. Here, we discuss two important applications of the RfR technique on nanoscale devices. first, RfR provides a method for fast (<100 ns) and broadband (in excess of 100 mHz) sensing of single-electron transistors (Sets) [5] and quantum point contacts (qPcs) [6], which are essential readout elements for promising new technologies such as spin quantum bits [7]– [9]. By contrast, the traditional methods of probing these types of devices by measuring changes in their conductance or resistance suffer from very limited band-width (<1 mHz) due to the high impedance of the devices and parasitic input capacitance of the sensing amplifier. in an RfR Set setup [5], the input Rf sine wave (with a frequency in the range of 10 8 –10 9 Hz) is reflected from a tank circuit , typically consisting of a lumped inductor and a parasitic capacitor to ground, acting as an impedance transformer , and the device under test (an Set or qPc) acting as the load. the main purpose of the inductor-capacitor (l-c) impedance transformer is to transform the high impedance of the device under test closer to a standard transmission line resistance , e.g., 50. X Because the impedance transformer typically used in an RfR setup is a resonant circuit, it also provides frequency selectivity, attenuates unwanted signals away from the resonant frequency, and suppresses " pink " /f 1 noise [10]. the second class of applications is the use of RfR-based spectroscopy to enable researchers to " look inside " devices to understand the intricate physical mechanisms of transport on the nanoscale. RfR in this case is used as a unique characterization tool for studying the properties of these devices and the materials of which they are composed. for this class of RfR application , speed and wide bandwidth are typically of lesser concern than obtaining the highest possible sensitivity. even small changes in the device capacitance, for example , as might arise from a single defect level, may be sufficient to produce a detectable signal. the role of the resonator is to increase the sensitivity of the reflected signal (i.e., the magnitude and phase) to changes in the device impedance, thereby easing the detection of small changes (e.g., caused by single-electron charging of an Set island or trapping/detrapping effects near it). the tools developed in the process of pursuing these two applications are complementary so that development in one leads to the progress in the other. for example, improvements in the charge sensitivity of the Rf Set qubit readout enhance the detection capabilities of the charged defect detecting technique.
    Full-text · Article · May 2015
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    ABSTRACT: We report the observation of an atomic like behavior from T=4.2K up to room temperature, in n and p type Omega-gate silicon nanowire (NW) transistors. For that purpose, we modified the design of a NW transistor and introduced long spacers between the source/drain and the channel, in order to separate the channel from the electrodes. The channel was made extremely small (3.4 nm in diameter with 10 nm gate length) with a thick gate oxide (7nm) in order to enhance the Coulomb repulsion between carriers, which can be as large as 200 meV when surface roughness promotes charge confinement. Parasitic stochastic Coulomb blockade effect can be eliminated in our devices by control voltages. Moreover, the quantum dot can be tuned so that the resonant current at T=4.2 K exceeds that at room temperature.
    No preview · Article · Apr 2015 · Nano Letters
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    ABSTRACT: We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively via in-situ gate-based radio frequency reflectometry, where one top-gate electrode is connected to a resonator. The latter removes the need for external charge sensors in quantum computing architectures and provides a compact way to readout the dispersive shift caused by changes in the quantum capacitance during interdot charge transitions. Here, we observe Pauli spin-blockade in the high-frequency response of the circuit at finite magnetic fields between singlet and triplet states. The blockade is lifted at higher magnetic fields when intra-dot triplet states become the ground state configuration. A lineshape analysis of the dispersive phase shift reveals furthermore an intradot valley-orbit splitting $\Delta_{vo}$ of 145 $\mu$eV. Our results open up the possibility to operate compact CMOS technology as a singlet-triplet qubit and make split-gate silicon nanowire architectures an ideal candidate for the study of spin dynamics.
    Full-text · Article · Apr 2015 · Nano Letters
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    ABSTRACT: Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
    Full-text · Article · Mar 2015 · Physical Review Applied
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    ABSTRACT: Electron spin qubits in silicon, whether in quantum dots or in donor atoms, have long been considered attractive qubits for the implementation of a quantum computer due to the semiconductor vacuum character of silicon and its compatibility with the microelectronics industry. While donor electron spins in silicon provide extremely long coherence times and access to the nuclear spin via the hyperfine interaction, quantum dots have the complementary advantages of fast electrical operations, tunability and scalability. Here we present an approach to a novel hybrid double quantum dot by coupling a donor to a lithographically patterned artificial atom. Using gate-based rf reflectometry, we probe the charge stability of this double quantum dot system and the variation of quantum capacitance at the interdot charge transition. Using microwave spectroscopy, we find a tunnel coupling of 2.7 GHz and characterise the charge dynamics, which reveals a charge T2 of 200 ps and a relaxation time T1 of 100 ns. Additionally, we demonstrate spin blockade at the inderdot transition, opening up the possibility to operate this coupled system as a singlet-triplet qubit or to transfer a coherent spin state between the quantum dot and the donor electron and nucleus.
    Full-text · Article · Mar 2015 · Physical Review X
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    ABSTRACT: This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed.
    No preview · Article · Feb 2015 · Solid-State Electronics
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    ABSTRACT: Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (∼3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.
    Full-text · Article · Feb 2015 · Solid-State Electronics
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    ABSTRACT: uantum computation requires a qubit-specific measurement capability to readout the final state of individual qubits. Promising solid-state architectures use external readout electrometers but these can be replaced by a more compact readout element, an in situ gate sensor. Gate-sensing couples the qubit to a resonant circuit via a gate and probes the qubit’s radiofrequency polarizability. Here we investigate the ultimate performance of such a resonant readout scheme and the noise sources that limit its operation. We find a charge sensitivity of 37 μe Hz−1/2, the best value reported for this technique, using the example of a gate sensor strongly coupled to a double quantum dot at the corner states of a silicon nanowire transistor. We discuss the experimental factors limiting gate detection and highlight ways to optimize its sensitivity. In total, resonant gate-based readout has advantages over external electrometers both in terms of reduction of circuit elements as well as absolute charge sensitivity.
    No preview · Article · Jan 2015 · Nature Communications

  • No preview · Article · Jan 2015 · IEEE Transactions on Electron Devices

  • No preview · Article · Jan 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: The less surface roughness scattering effects, owing to the unique operation principle, in junctionless nanowire transistors (JLT-NW) were shown by low-temperature characterization and 2D numerical simulation results. This feature could allow a better current drive under a high gate bias. In addition, the dominant scattering mechanisms in JLT-NW, with both a short (LM = 30 nm) and a long channel (LM = 10 μm), were investigated through an in-depth study of the temperature dependence of transconductance (gm) behavior and compared to conventional inversion-mode nanowire transistors.
    Full-text · Article · Dec 2014 · Applied Physics Letters

Publication Stats

758 Citations
204.72 Total Impact Points

Institutions

  • 2014-2015
    • University of Grenoble
      Grenoble, Rhône-Alpes, France
  • 2004-2015
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2012-2014
    • Atomic Energy and Alternative Energies Commission
      • Laboratoire d'Électronique des Technologies de l'Information (LETI)
      Fontenay, Île-de-France, France
  • 2013
    • Korea University
      • Department of Electrical Engineering
      Sŏul, Seoul, South Korea
  • 2000-2006
    • Université Paris-Sud 11
      • Institut d'Electronique Fondamentale
      Orsay, Île-de-France, France
  • 2002
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France