[Show abstract][Hide abstract] ABSTRACT: A defect which occurs at the corner of the metal/n+ contact bottom in direct contact (DC) of dynamic random access memories (DRAMs) with 100 nm technology and below is reported for the first time. The defect consists of Si stacking faults with a Si  zone axis and contains diffused titanium. The DC defect was responsible for high n+/p leakage current which increased with decreasing contact size. The defect can be completely removed by applying 700-900°C rapid thermal process (RTP) immediately after chemical vapor deposition (CVD)-Ti/TiN deposition, which transforms the deposited titanium to C54 titanium silicide. It is suggested that the generation of the DC defects is related to the incomplete phase transformation of titanium silicide.
No preview · Article · Apr 2004 · Japanese Journal of Applied Physics
[Show abstract][Hide abstract] ABSTRACT: The new barrier metal structure using selective wetting layer was proposed. This process using physical vapor deposition (PVD) Ti as the controlling layer for conformal chemical vapor deposition (CVD) Al layer shows an excellent filling capability for deep small contact and good electrical properties as well as the remarkable surface morphology, which can be applied for the new metallization process such as metal contacts and via holes filling.
[Show abstract][Hide abstract] ABSTRACT: Plasma-induced damage by the PECVD-Ti process on the leakage current of sub-5 nm gate oxide was investigated. The plasma conditions during the deposition of PECVD-Ti critically affected characteristics of the gate oxide such as the leakage current and the breakdown voltage. Lowering of plasma power in a deposition step improves the gate oxide properties but cannot clearly reduce all gate oxide failure. According to plasma damage monitoring analysis, a large plasma damage during the plasma ignition step was observed, which indicates that failure of the gate oxide was due to the unbalanced plasma ignition in the deposition step. It is very important to optimize process parameters and to control system conditions to prevent the unbalanced plasma ignition during the PECVD-Ti process.
[Show abstract][Hide abstract] ABSTRACT: The implementation of W bit-line enabled the integration of n+ and p+ common contact process at bit-line level. Despite the advantages of the common contact process such as chip-area reduction and elimination of the burden associated with MC dry etch, the immediate implementation of the common contact is difficult due to large increase of p+ contact resistance with high thermal budget capacitor process. The results of the present investigation indicate that the thickness of TiSi<sub>2</sub> layer must be minimized in order to prevent the out-diffusion of boron into silicide layer. However, simply reducing the thickness of TiSi<sub>2</sub> presents another problem since it leads to a discontinuous layer of TiSi<sub>2</sub>. Heavily increasing the dosage of p+ plug implantation, which is another way of preventing the depletion of boron dopants, resulted in degradation of p+ contact resistance. Therefore, the dopant out-diffusion alone cannot explain the degradation of p+ contact resistance. In order to minimized the thickness of TiSi<sub>2</sub>, enhanced nitridation after deposition of PECVD-Ti was tested and resulted in effective reduction of the p+ contact resistance by 25%. The TEM and SIMS analysis showed that the additional growth of TiSi<sub>2</sub> during high thermal budget post annealing was suppressed by the enhanced nitridation. The mechanism responsible for reducing the p+ contact resistance by the enhanced nitridation is attributed to the prevention of the dopant depletion at the interface between TiSi<sub>2</sub> and Si due to the suppressed formation of additional TiSi<sub>2</sub>
[Show abstract][Hide abstract] ABSTRACT: The effect of the initial steps in PECVD-Ti process is investigated for the optimization of TiSi<sub>x</sub> formation. A remarkable difference in TiSi<sub>x</sub> formation is observed between pre-plasma and pre-TiCl<sub>4</sub> treatment in which the initial steps start with H<sub>2</sub> gas with plasma and TiCl<sub>4</sub> gas without plasma. TiCl<sub>4</sub> pre-treatment in the PECVD-Ti process is compared with H<sub>2</sub> plasma pre-treatment especially for low aspect ratio contacts. PECVD-Ti films with H<sub>2</sub> plasma pre-treatment results in accumulation of Cl impurities at the interface between Si and TiSi<sub>x</sub>, and subsequently results in thinner TiSi<sub>x</sub> and higher contact resistance. With the optimized TiCl <sub>4</sub> pretreatment, excellent electrical characteristics are obtained in sub-0.2 μm bit line contacts