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Publications (6)4.3 Total impact

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    ABSTRACT: In this paper, we have developed a new floating-gate-type Flash cell compact model based on the channel potential by using PSP metal-oxide-semiconductor description. Cell-to-cell coupling, Fowler-Nordheim tunneling, and new leakage current formulas have been implemented on Verilog-A compact model. The channel potential calculation of the PSP model enables accurate modeling of channel coupling and leakage currents which are associated with the boosted channel. In addition, the model parameter extraction procedure through 3-D technology computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of sub-20-nm nand cells.
    No preview · Article · Dec 2012 · IEEE Transactions on Electron Devices
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    ABSTRACT: A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout variations by applying the simple physics-based equations to model these parameters. The accuracy of the model is verified using numerical TCAD simulation results and measurements under full range of temperature and bias conditions. The compact model for the circuit simulation can be efficiently used to predict the effects of process and layout variations on the circuit characteristics.
    Preview · Conference Paper · Oct 2010
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    ABSTRACT: A unified compact model to predict the performance degradation of a circuit due to the electrical gate oxide stress is developed and verified by experimental results. Hot carrier injection (HCI), off-state (OS), and Fowler-Nordheim (FN) degradations can be described by a single formula which models the trap generation over the stress time and voltage. With the proposed model, the propagation delay (tPD) degradation of a ring oscillator is reproduced with the accuracy of more than 90%. It is found that OS plays major role in the tPD degradation rather than HCI, while the component ratio of HCI is getting larger as the frequency increases.
    No preview · Conference Paper · Jan 2008
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    ABSTRACT: A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.
    Full-text · Article · Jan 2003 · IEEE Transactions on Nanotechnology
  • Chang-Sub Lee · Gi-Young Yang
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    ABSTRACT: An efficient modeling methodology for abnormally structured MOS transistors, which have irregular contacts, polygonal diffusion areas, or curved gate patterns, is presented. The DC Performances of the abnormal transistors are worse compared to those of normal transistors in general. Therefore, it is important for designers to model the current degradation effects of the abnormal transistors with keeping the physical meaning at the circuit simulation stage. Contrary to the previous method utilizing a 3D device simulator which needs a sophisticated calibration work and long simulation times, only the 3D Poisson solver is employed to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. In this paper, overall flow of the proposed method, which needs no calibration work and short simulation time, is discussed. Applications to the abnormal transistors with U-shaped and tilted gates in the 0.17 um DRAM design are performed and the validity of the proposed methodology is examined experimentally. We expect that the easiness of the proposed method guarantees an efficient reflection of the current degradation effect, even with frequent layout modifications in the VLSI designs.
    No preview · Conference Paper · Mar 2002
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    ABSTRACT: An efficient modeling methodology for abnormally structured MOS transistors is presented. Contrary to the previous method utilizing a 3D device simulator, only the 3D Poisson solver is used to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. For the frequent modifications of the layout design, the easiness of the proposed method guarantees the efficient reflection of the current degradation effect in circuit simulation. This method is applied to 0.17 μm DRAM process and the good agreements with the measured data are examined.
    No preview · Conference Paper · Feb 2002