L. Pantisano

imec Belgium, Louvain, Flemish, Belgium

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Publications (175)206.26 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We proposed a new, simpler, and fully BEOL CMOS-compatible TiN/HfO"2/TiN RRAM stack using the Plasma Enhanced Atomic Layer Deposition (PEALD) for the top-electrode TiN processing, demonstrating attractive bipolar switching properties (by positive RESET voltage to the PEALD TiN) in a functional size down to 2275nm^2 (35nmx65nm). Stable switching was observed between a High-Resistive State HRS (~1M@?) and a Low-Resistive State LRS (~100k@?), using a low program current of ~1@mA. Two different LRS states can be obtained depending on the current compliance (CC) during SET switching, either 100@mA (high-CC LRS) or 10@mA (low-CC LRS), resulting, respectively in LRS resistances of 10k@? or 100k@?. The projected retention stability of low-CC LRS is >=10years at 80^oC, which is the retention minimum of the TiN/HfO"2/TiN RRAM stack. The temperature-dependent resistance showed a non-metallic behavior for the low-CC LRS state (~100k@?), suggesting gentle filament formation.
    No preview · Article · Dec 2013 · Microelectronic Engineering
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    ABSTRACT: In this work we provide a comprehensive evaluation of a novel, low-resistance Co-Al alloy vs W to fill aggressively scaled gates with high aspect-ratios [gate height (H-gate) similar to 50-60 nm, gate length (L-gate) >= 20-25 nm]. We demonstrate that, with careful liner/barrier materials selection and tuning, well-behaved devices are obtained, showing: tight gate resistance (R-gate) distributions down to L-gate similar to 20 nm, low threshold voltage (V-T) values, comparable DC and bias temperature instability (BTI) behavior, and improved RF response. The impact of fill-metals intrinsic stress, including the presence of occasional voids in narrow W-gates, on devices fabrication and performance is also explored. (C) 2013 The Japan Society of Applied Physics
    No preview · Article · Apr 2013 · Japanese Journal of Applied Physics
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    ABSTRACT: The impact of high-mobility channel materials such as SiGe, Ge, III-V and novel device architectures on the low-frequency noise behavior of 22nm and below CMOS transistors is reviewed. To study the impact on the noise, a comparison is made with planar implant-free quantum well (IFQW) pMOSFETs, exhibiting mainly 1/f noise which is governed by mobility fluctuations, based on the behavior of the normalized current PSD versus the channel current in linear operation. Contrasting low frequency (LF) noise spectra and power spectral density (PSD) are seen for (110) and (100) SiGe p-channel bulk FinFETs. The highest hole mobility is obtained for the (110) based SiGe-channel pMOSFETs, which can be ascribed to the favorable channel orientation compared with (100) silicon substrates. Additional GR noise variability can be induced by device-to-device variations in the threshold voltage, as this will equally modify the quasi-Fermi level with respect to the trap level for the same operation voltages.
    No preview · Article · Mar 2013
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    ABSTRACT: In this work, an extensive characterisation of intrinsic amorphous silicon (a-Si) passivation layers deposited on n- and p-type silicon is reported. Low temperature capacitance-voltage measurements are utilised to enable parameter extraction from the c-Si/a-Si interface and a-Si bulk. Electron spin resonance enables atomic identification of defects present. Results reveal the presence of electrically active defects at the c-Si/intrinsic a-Si interface (∼1x1012 cm-2), and throughout the amorphous silicon layer bulk (∼8x1016 cm-3), which are atomically identified as Pb0 centres and D centres silicon dangling bond defects, respectively. The value of this work is the atomic identification of these defects in this stack, coupled with their electrical activity. That they can be detected by these techniques demonstrates the power of the methodology used to assess and quantify these defects. Therein lies the significance of this work: a methodology capable of fundamentally optimising amorphous silicon processing from an atomic perspective.
    Full-text · Article · Dec 2012
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    ABSTRACT: A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.
    No preview · Conference Paper · Dec 2012
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    ABSTRACT: An overview is given on the impact of the implementation of high-mobility channel materials and novel device architectures on the low-frequency (LF) noise behavior of 22 nm and below CMOS transistors. It will be shown that a similar 1/f noise power spectral density (PSD) can be achieved for SiGe-channel planar and bulk FinFET devices, whereby mobility fluctuations are dominant. At the same time, it is demonstrated that processing-induced Generation-Recombination (GR) noise can yield a strong device-to-device variability in the PSD. This is illustrated for both bulk FinFETs and thin-film ultra-thin buried oxide (UTBOX) Silicon-On-Insulator (SOI) MOSFETs. A model is presented for the LF noise in narrow, fully-depleted (FD) device structures, allowing the extraction of the oxide trap density profiles and silicon film GR center parameters. This model explains the occurrence of Lorentzian GR noise with gate voltage dependent parameters in planar or vertical FD devices and at the same time points out a new source of noise variability, which becomes important for future bulk FinFET technology nodes.
    Full-text · Conference Paper · Dec 2012
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    ABSTRACT: Physical and electrical characteristics of Metal–Insulator–Metal TiN/HfO2/TiN capacitors have been investigated. A detailed study using internal photoemission and trap assisted transport simulation enabled the extraction of relevant important parameters like barrier height (∼2.5 eV) for both injecting interfaces, optical energy gap (∼5.6 eV), as well as trap density and energy position within the bandgap (NT = 3 × 1019 cm−3; σT = 1 × 10−14 cm2; ET = 2.0–2.6 eV below the bottom of the HfO2 conduction band). The extracted parameters surprisingly showed striking similarities with HfO2 deposited on a Si surface, i.e., in MOSFET process flow. Additionally, Constant Voltage Stress showed a leakage current increase, preferentially at low voltage. This can be explained by preexisting defect precursors (likely related to oxygen vacancies) or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.
    No preview · Article · Jul 2012 · Microelectronic Engineering
  • Lionel Trojman · Luigi Pantisano · Lars-Ake Ragnarsson
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    ABSTRACT: Low- and high-field transports are investigated for $\hbox{HfO}_{2}$ -based MOSFETs with ultrathin equivalent oxide thickness (UTEOT) $(EOT = \hbox{6.4}{-}\hbox{8.4}\ \hbox{\rm{\AA}})$ achieved by a remote interface layer (IL) scavenging method. A detailed comparison with a SiON reference demonstrates none of the detrimental effects from $\hbox{HfO}_{2}$-related Coulomb nor phonon additional scattering on the high-field velocity. Increased surface roughness may reduce the high-field velocity by 20% for the device with the thinnest IL. This is explained by an increase of the backscattering which reduces the ballistic efficiency for the shortest devices $(L_{\rm MET} = \hbox{25}\ \hbox{nm})$. However, the on-state current $(I_{\rm ON})$ for UTEOT devices has the best performance at a given high-lateral-field velocity. Therefore, EOT scaling remains a valid tool for $I_{\rm ON}$-performance improvement for CMOS scaling also with new architectures and substrates.
    No preview · Article · Jul 2012 · IEEE Transactions on Electron Devices
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    ABSTRACT: A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on $\hbox{HfO}_{2}$ dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics. FinFETs with an ALD TiN gate exhibit better NBTI and PBTI lifetimes than those with a PVD TiN gate. In addition, the dependence of fin width on NBTI reliability appeared to be worse with narrower fins, whereas PBTI reliability improves.
    No preview · Article · Jul 2012 · IEEE Electron Device Letters
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    ABSTRACT: Beside the VTH-tunability, a raised SiGe S/D module offers higher LG-scalability than an embedded SiGe S/D in SiGe-IFQW pFETs. In-depth transport study of record performing 1.5mA/μm-ION strained-SiGe IFQW pFETs reveals that mobility improvement is still the key performance booster whereas LG-scaling has limited impact.
    No preview · Conference Paper · Jun 2012
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    ABSTRACT: In this work, we present a detailed electrical characterization of TiN\HfO2\Hf\TiN RRAM elements, and show for the first time the intrinsic switching characteristics in the low current operation regime (100uA till few uA's) of small scaled cells (20nm) under DC and fast ramps (up to 1MV/s) condition, using a newly proposed 2R test structure. The main characteristic parameters of the SET and RESET switching are defined and their speed dependence is characterized. Resistance decrease during SET is observed to occur at a constant voltage Vtrans, while symmetrically RESET process starts at -Vtrans. With reducing operation current, mean values of the symmetric SET and RESET transition voltages remain unchanged but their spread strongly increases. The actual I-V characteristics show discrete current jumps and non-linear quantum-mechanical conduction is evidenced and more pronounced at smaller currents. Increasing the ramp rate increases the SET and RESET transition voltage logarithmically with a concomitant reduction of the HRS resistance. These measurements allow for a better insight and understanding of the dynamic switching properties in low-current, ultra-scaled RRAM cells.
    No preview · Article · May 2012
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    ABSTRACT: Low-temperature (77 K) capacitance-voltage measurements are proposed as a technique to quantify the densities of traps in c-Si/a-Si:H heterojunction solar cell structures. By comparing the inferred trap densities to the results of electron spin resonance spectroscopy, we found that the dangling bonds of silicon atoms at the surface of the (100) Si substrate (P-b0 centers) and in a-Si: H layer (D-centers) provide the most significant contributions to the density of traps. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3698386]
    Full-text · Article · Apr 2012
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    ABSTRACT: NBTI characteristics of p-FinFET with TiN metal gates deposited by ALD or PVD method have been investigated in detail. NBTI lifetime of ALD-TiN gate device was better than that of PVD TiN gate device. The differences were primarily attributed to the differences in the thickness and quality of interfacial SiO2 layer which was affected by an oxygen scavenging reaction of TiN layer. Also, NBTI characteristics were degraded at narrower FinFET in both ALD and PVD devices as the contribution from sidewall (110) region increased.
    No preview · Conference Paper · Apr 2012
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    ABSTRACT: This paper discusses the low-frequency noise behavior of SiGe-channel bulk FinFETs processed on (100) and (110) Si wafers. A comparison is also made with planar SiGe-channel pMOSFETs. It is shown that for devices with carriers confined in the quantum well, only 1/f noise is observed, dominated by mobility fluctuations. Surprisingly, SiGe pMOSFETs fabricated on (110) Si wafers exhibit the highest mobility but also the highest 1/f noise, corresponding with trapping/detrapping. This is also consistent with the density of interface traps extracted from charge pumping measurements.
    Full-text · Conference Paper · Jan 2012
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    ABSTRACT: Introduction: Series resistance (Rseries) is a crucial factor for technology optimization and benchmarking [1–3]. Rseries is typically extracted in the bias conditions where Rseries dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or Rseries. For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any Rseries extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several Rseries extraction techniques [1–3] and then use the best of both to gain new insights on the finfet and SiGe technology.
    No preview · Article · Jan 2012
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    ABSTRACT: We proposed a Mo/SiOx/Pt resistive random access memory (RRAM) device as an alternative to static random ac- cess memory (SRAM) devices for field-programmable gate array (FPGA) applications. In order to evaluate the feasibility of our RRAM device for FPGA applications, we utilized an RRAM device + inverter structure and confirmed its successful opera- tion under various operational schemes, multilevel operation by controlling bias condition, and immunity against read disturbance and a retention test at high temperature. From the nonvolatile and reliable characteristics of our RRAM device, unlike that of SRAM devices, it holds promise to enable reconfigurable logic ap- plications with significantly reduced logic-gate density and power consumption. Index Terms—Field-programmable gate array (FPGA), recon- figurable logic, resistive random access memory (RRAM).
    No preview · Article · Dec 2011 · IEEE Electron Device Letters
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    ABSTRACT: Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al2O3, ZrO2 and HfO2 as well as their mixtures. Very promising results have been reported world-wide. Here, however, we show that there are a number of issues related to materials and electrical characteristics as well as to processing which are not always recognized and that necessitate more work to find solutions. Among these are problems with density, interface layer growth and island formation which are clearly related to the deposition process. Also thermal instabilities as well as interactions between the high-k material and poly-Si need attention. Further possible show-stoppers are electrical reliability issues and strongly reduced carrier mobility.
    No preview · Article · Nov 2011 · International Journal of High Speed Electronics and Systems
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    ABSTRACT: The band alignment between a dielectric and a metal gate is crucial as it controls the MOSFET threshold voltage as well as the leakage in metal–insulator–metal (MIM) structure. In the ideal Schottky–Mott model the barrier height should be controlled only by the workfunction and the electron affinity of the materials considered. However, this seems the case only for few insulating materials other than SiO2 (i.e., Fermi level pinning).The most popular explanation invokes metal-induced gap states (MIGS), where electron states from the bulk of a metal tails into the insulator. The MIGS hypothesis explains a rather large series of experimental results and, importantly, predicts that the MI barrier height will mostly be controlled by the energy distribution of electron states in the bulk of the contacting metal and dielectric. In this paper, we analyze the band alignment of contacting metal (TiN) and dielectric (HfO2) by using internal photoemission. It will be shown that defects in the dielectric rather than MIGS control the barrier height.Graphical abstractModulation of barrier height up to 0.8 eV for the same TiN/HfO2 injected interface.Highlights► Modulation of defects in HfO2 by using an oxygen scavenger (i.e., Hf). ► Modulation of barrier height up to 0.9eV for the same HfO2/TiN deposition chemistry and interface. ► Defect spectroscopy reveals the energy position of these defects at 0.6–0.7eV below the HfO2 conduction band.
    No preview · Article · Jul 2011 · Microelectronic Engineering
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    ABSTRACT: Electron barrier height measurements at TiN <sub> x </sub>/ HfO <sub>2</sub> interfaces in metal-insulator-metal structures using internal photoemission of electrons reveal a significant (≈1 eV, i.e., about 1/3 of the total barrier height) influence of the opposite electrode material, i.e., Hf versus TiN <sub> x </sub> . This effect is suggested to be caused by oxygen scavenging from HfO <sub>2</sub> by the opposite Hf electrode resulting in generation of positive charges in the oxide above the metal electrode surfaces. Such a considerable interface dipole component demonstrates a principle that may be used to tune the barrier.
    Full-text · Article · Apr 2011 · Applied Physics Letters
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    ABSTRACT: gwagiro (Oryong-dong), Buk-gu, Gwangju 500-712 Republic of Korea 3 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Electron barrier height measurements at TiN x / HfO 2 interfaces in metal-insulator-metal structures using internal photoemission of electrons reveal a significant 1 eV, i.e., about 1/3 of the total barrier height influence of the opposite electrode material, i.e., Hf versus TiN x . This effect is suggested to be caused by oxygen scavenging from HfO 2 by the opposite Hf electrode resulting in generation of positive charges in the oxide above the metal electrode surfaces. Such a considerable interface dipole component demonstrates a principle that may be used to tune the barrier. © 2011 American Institute of Physics. doi:10.1063/1.3570647 The physical mechanisms determining the height e of the energy barrier for electrons at metal/insulator MI inter-faces have been debated for decades as these barriers have direct impact on the functionality of semiconductor devices. The ideal Schottky–Mott model predicts a simple relation-ship of the barrier height to the work function WF of the metal and the electron affinity of the insulator ins : e =WF− ins . Unfortunately, this appears to be the case only for a few insulating materials, such as SiO 2 ; 1,2 Other insula-tors show either a weaker e variation with changing metal WF or no correlation at all. 3 To explain this phenomenon, commonly referred to as Fermi level pinning, a number of models have been proposed based on the idea of breaking the electrical neutrality at the interface by introducing additional charges, thus leading to an interface dipole-type barrier com-ponent. Yet, the most popular concept invokes metal-induced gap states MIGS, a hypothesis that suggests "tailing" of electron states from the bulk of the metal across the interface plane into the insulator. 4 This hypothesis allows one to ex-plain reasonably well a large series of experimental results 5–7 and, importantly, predicts that the MI barrier height will mostly be controlled by the energy distribution of electron states in the bulk of the contacting solids. Indeed, the latter is observed at semiconductor/insulator interfaces 3 but the avail-able experimental results for metal/high-permittivity oxide structures expose a considerable scatter of the results 3 as well as sensitivity to the particular processing applied, suggestive of an additional contribution to the MI barrier height. 8 Taken together with the arguments countering the MIGS hypothesis, 9 these discrepancies would stimulate experimen-tal evaluation of the additional MI barrier components. The traditional way to study the MI barrier consists in monitoring the barrier height dependence on the WF of the contacting metal. 1–3 However, the interface chemistry, com-position and variability may depend on the chemical reactiv-ity of metals, particularly if thermal processing is involved. 8 In this work we excluded this factor by monitoring e
    No preview · Article · Mar 2011 · Applied Physics Letters

Publication Stats

2k Citations
206.26 Total Impact Points


  • 2001-2013
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flemish, Belgium
  • 2012
    • Università della Calabria
      Rende, Calabria, Italy
    • Gwangju Institute of Science and Technology
      • Department of Nanobio Materials and Electronics
      Gwangju, Gwangju, South Korea
  • 1998-2000
    • University of Padova
      • Department of Information Engineering
      Padua, Veneto, Italy