[Show abstract][Hide abstract] ABSTRACT: Thermal radiometers such as proposed for the Europa Clipper flyby mission  require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi-Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm 2 /mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.
[Show abstract][Hide abstract] ABSTRACT: Introduction: Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle flu-ence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16-bit sigma-delta analog-digital converter (SDADC) and a controller. The MCD was evaluated at Goddard Space Flight Center's and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm 2 /mg and 50 Mrad (Si) respectively. Figure 1. MCD ASIC (5mm x 5mm)
[Show abstract][Hide abstract] ABSTRACT: We describe one key hardware development at Goddard that is undergoing maturation for risk mitigation, a radiation hardened by design (RHBD) multi-channel digitizer (MCD) Application Specific Integrated Circuit (ASIC) for thermopile array readout.
[Show abstract][Hide abstract] ABSTRACT: The original and primary task of self-test program Smalley3 was independent verification of the logic design of the LOLA DU (lunar orbiter laser altimeter digital unit) microprocessor. Tasks were added to verify continuing correct operation of this central processing unit (CPU) under margin testing for supply voltage, ambient temperature, and clock frequency. Finally, an on-orbit diagnostic task was added so that any malfunctions of LOLA in lunar orbit can be identified as faults in, or not in, the CPU. The Lunar Reconnaissance Orbiter spacecraft will be launched to the Moon in 2009 with six scientific instruments including LOLA, each containing an embedded microprocessor to perform real-time subsystem control calculations. LOLA's CPU is a small, custom-designed processor, designed to meet the mission requirements while minimizing resources. This 8-bit machine is essentially code compatible with Intel's 8085 but is implemented in modern technology, an advanced, radiation-hardened 0.15 mum gate array, with the only logic element types being a 4:1 multiplexor and a flip-flop. This paper explains the fundamental structure of the verification task, shows how particular instructions are verified, presents a high-coverage scheme for detecting inadvertent RAM alteration, describes subsystem testing of RAM, and reviews the results of the verification effort. Some infamous CPU design flaws from both the commercial industry and aerospace flight control systems are discussed.
[Show abstract][Hide abstract] ABSTRACT: The single event effects and hardening of a 0.15 μm antifuse FPGA, the AX device, were investigated by beam test and computer simulation. The beam test showed no permanent damage mode. Functional failures were observed and attributed to the upsets in a control logic circuit, the startup sequencer. Clock upsets were observed and attributed to the single event transients in the clock network. Upsets were also measured in the user flip-flop and embedded SRAM. The hardening technique dealing with each upset mode is discussed in detail. SPICE and three-dimensional mixed-mode simulations were used to determine the design rules for mitigating the multiple upsets due to glancing angle and charge sharing. The hardening techniques have been implemented in the newly fabricated RTAXS device. Preliminary heavy-ion-beam test data show that all the hard-wired hardening solutions are working successfully.
No preview · Article · Jan 2004 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: Architecture and process, combined, significantly affect the hardness of programmable technologies. The effects of high energy ions, ferroelectric memory architectures, and shallow trench isolation are investigated. A detailed single event latchup (SEL) study has been performed.
Preview · Article · Jan 2000 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.
Preview · Article · Jan 2000 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: The startup current in an antifuse field programmable gate array
(FPGA) device, A1280A, is investigated in the context of ionizing
radiation effects. If properly measured, a radiation induced startup
transient (RIST) can be identified after certain amount of irradiation.
RIST increases with total dose (TID), and is strongly dependent on the
dose rate. Room-temperature biased annealing for few days can reduce
RIST to a very low level. A transistor-level mechanism is proposed to
elucidate the origin of RIST. The ionization induced leakage in the NMOS
diode is believed to be the root cause. The degradation of the ramping
speed of the charge pump causes RIST when powering up the device. SPICE
simulation was also performed to demonstrate the slow down of the
ramping speed by the leakage in the NMOS diode. In typical low-dose-rate
space environments, RIST is not the limiting factor for the total dose
[Show abstract][Hide abstract] ABSTRACT: Manufacturers of field programmable gate arrays (FPGAs) take
different technological and architectural approaches that directly
affect radiation performance. Similar technological and architectural
features are used in related technologies such as programmable
substrates and quick-turn application specific integrated circuits
(ASICs). After analyzing current technologies and architectures and
their radiation-effects implications, this paper includes extensive test
data quantifying various devices' total dose and single event
susceptibilities, including performance degradation effects and
temporary or permanent re-configuration faults. Test results will
concentrate on recent technologies being used in space flight electronic
systems and those being developed for use in the near term. This paper
will provide the first extensive study of various configuration memories
used in programmable devices. Radiation performance limits and their
impacts will be discussed for each design. In addition, the interplay
between device scaling, process, bias voltage, design, and architecture
will be explored. Lastly, areas of ongoing research will be discussed
Preview · Article · Jan 1998 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: Irradiations and subsequent failure analyses were performed to
investigate single event dielectric rupture (SEDR) in Actel FPGAs as a
function of ion LET (linear energy transfer), angle, bias, temperature,
feature size, and device type. The small cross sections imply acceptably
low risk for most spacecraft uses
[Show abstract][Hide abstract] ABSTRACT: Gamma irradiation and annealing of a large number of Actel FPGAs
with in-situ current measurements were performed. Lot-to-lot,
part-to-part, and burn in variations were measured. Findings include a
catastrophic failure mechanism and minimal dose rate effects
[Show abstract][Hide abstract] ABSTRACT: Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.< >
Preview · Article · Jan 1995 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: A review of the ongoing efforts to improve the applicability of standard CMOS COTS devices to space environments. Discussions will center on specific design and processing techniques that will include methods of increasing total dose survivability levels and decreasing single event upset susceptibility. These concepts were guided by observations and measurements made on the Actel OTP FPGAs through seven process generations (2.0 um to 0.35 um). Both one-time and reprogrammable FPGA futures will be reviewed.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed.
[Show abstract][Hide abstract] ABSTRACT: The product development of a total dose hardened, QML antifuse field programmable gate array (FPGA) is presented. A commercial design, the Actel A1020B, is fabricated by a radiation-hard process to meet total dose hardening requirements for space system designs. Modification of the device, process and circuit design was done to optimize the wafer yield, programmability, and single event effect (SEE) susceptibility. Extensive single event upset (SEU) tests were performed to study the sensitivity of the clock circuit. Special DUT (device under test) design to count the upset rates due to the clock circuit was implemented. SEU rate prediction was also done for a typical geostationary orbit to evaluate the upsets due to the clock circuit.
[Show abstract][Hide abstract] ABSTRACT: Traditionally, many groups have performed total dose testing using a radiation step protocol. Two generations of an in situ measurement system is described, for both parametric and functional testing. Insights into modern device's behavior and the importance of this testing approach is discussed. An approach for a third generation in situ system is then presented.
[Show abstract][Hide abstract] ABSTRACT: The potential of a FLASH memory based FPGA, ProASIC, is investigated for space applications. The configuration cell is using a state-of-art 0 .25μm FLASH technology. The technology and architecture are introduced. The manifestation of total dose and single event effects is discussed.
[Show abstract][Hide abstract] ABSTRACT: An SEU-hardened flip-flop has been designed and developed for antifuse FPGA application. Design and application issues, testability, test methods, simulation and results are discussed.