Stefan Schürmans

RWTH Aachen University, Aachen, North Rhine-Westphalia, Germany

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Publications (7)1.98 Total impact

  • Stefan Schürmans · Diandian Zhang · Rainer Leupers · Gerd Ascheid · Xiaotao Chen
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    ABSTRACT: Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.
    No preview · Article · Jun 2014
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    ABSTRACT: Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) for runtime management called OSIP on two platform paradigms: shared and distributed memory. For the former, a generic bus is used as interconnect. For distributed memory, a Network-on-Chip (NoC) is used. The effects of OSIP and the communication architecture are jointly investigated from the system point of view, based on a broad case study with real applications (an H.264 video decoder and a digital receiver for wireless communications) and a synthetic benchmark application.
    No preview · Article · Jan 2014
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    ABSTRACT: Programming heterogeneous MPSoCs (Multi-Processor Systems on Chip) is a grand challenge for embedded SoC providers and users today. In this paper, we argue the need for and significance of positioning the language and tool design from the perspective of practicality to address this challenge. We motivate, describe and justify such a practical design of a compilation framework for heterogeneous MPSoCs targeting the domain of streaming applications, named MAPS (MPSoC Application Programming Studio). MAPS defines a clean, light-weight C language extension to capture streaming programming models. A retargetable source-to-source compiler is developed to provide key capabilities to construct practical compilation frameworks for real-world, complex MPSoC platforms. Our results have shown that MAPS is a promising compiler infrastructure that enables programming of heterogeneous MPSoCs and increases productivity of MPSoC software developers.
    No preview · Article · Jan 2013 · Parallel Computing

  • No preview · Conference Paper · Jul 2012
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    ABSTRACT: With the advent of multi-processor systems on chip (MPSoCs) and due to the complexity and variety of modern wireless standards, academia and industry are moving towards software defined radio (SDR) solutions. It is the goal of the SDR approach to allow designers to describe a radio standard or waveform by means of a high level language. This allows faster waveform development cycles and makes it easier to migrate waveforms across different platforms. Out of many software paradigms, component-based software engineering (CBSE) is an attractive match for SDR, especially for baseband applications. It abstracts waveforms in the traditional way algorithm designers think of their applications and guarantees a high degree of portability. However, existing CBSE approaches for SDR have not been able to close the gap between specification and implementation so as to achieve the computational performance and the energy efficiency of handcrafted solutions. The main reason for this gap is that these flows rely on traditional compilers to lower the high level specification to the platform. The work presented in this paper builds on the Nucleus Concept (Ramakrishnan et al., IEEE Military Communications Conference (MILCOM 2009) [28]) in which computationally intensive kernels and their implementation characteristics on the target platform are known. This information allows a tool to close the performance gap, and thus enables efficient component-based SDR development. In this paper we present such a flow and its supporting environment, which includes state-of-the-art tools for system level design. The flow is demonstrated on a MIMO OFDM transceiver. KeywordsSoftware defined radio–MPSoC programming–Scheduling– Mapping–Real time systems–Data flow graphs–MIMO–OFDM
    No preview · Article · Dec 2011 · Analog Integrated Circuits and Signal Processing

  • No preview · Conference Paper · Dec 2010
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    S. Schürmans · E. Weingärtner · T. Kempf · G. Ascheid · K. Wehrle · R. Leupers
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    ABSTRACT: Nowadays, the development of embedded system hardware and related system software is mostly carried out using virtual platform environments. The high level of modeling detail (hardware elements are partially modeled in a cycle-accurate fashion) is required for many core design tasks. At the same time, the high computational complexity of virtual platforms caused by the detailed level of simulation hinders their application for modeling large networks of embedded systems. In this paper, we propose the integration of virtual platforms with network simulations, combining the accuracy of virtual platforms with the versatility and scalability of network simulation tools. Forming such a hybrid tool-chain facilitates the detailed analysis of embedded network systems and related important design aspects, such as resource effectiveness, prior to their actual deployment.
    Full-text · Conference Paper · Jun 2010