C. Hobbs

Sematech Inc., New York, New York, United States

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Publications (96)

  • Conference Paper · May 2015
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    [Show abstract] [Hide abstract] ABSTRACT: III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (R ext) be minimized. Among the different components of R ext , contact resistance (R C), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower R C. However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low R C. In addition, a " silicide-like " metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these R C reduction options and present some of our recent results on contact/junction engineering to lower R C in III-V MOSFETs.
    Full-text available · Article · Apr 2015 · ECS Transactions
  • [Show abstract] [Hide abstract] ABSTRACT: We report on Lg = 80-nm trigate quantumwell InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with record combination of subthreshold swing, transconductance and ON-current performance. The device features a multilayer cap design, bilayer Al2O3/HfO2 (0.7/2 nm) gate-stack by atomic layer deposition and dry etched In0.53Ga0.47As fin. An Lg = 80-nm trigate MOSFET with fin-width (Wfin) = 30 nm and fin-height (Hfin) = 20 nm exhibits excellent performance, such as ON-resistance (RON) = 220 Ω-μm, subthreshold swing (S) = 82 mV/dec, and drain-induced-barrier lowering = 10 mV/V at VDS = 0.5 V. Besides, the device exhibits record values of maximum transconductance (gm_max) = 1800 μS/μm and ION = 0.41 mA/μm at VDS = 0.5 V, and a record combination of gm_max and S in any III-V nonplanar MOSFET technology.
    Article · Mar 2015 · IEEE Electron Device Letters
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    [Show abstract] [Hide abstract] ABSTRACT: In 0.53 Ga 0.47 As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In 0.53 Ga 0.47 As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III–V on Si sample and the control that perform similarly below 8.6 × 10 −10 cm 2. The existence of a critical device area suggests the potential to utilize III–V on Si for other deeply scaled tunnel devices. Index Terms— III–V on Si, Esaki diode, excess current, negative differential resistance (NDR), tunnel junction.
    Full-text available · Article · Feb 2015 · IEEE Transactions on Electron Devices
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    Chadwin D. Young · Arnost Neugroschel · Kausik Majumdar · [...] · Chris Hobbs
    [Show abstract] [Hide abstract] ABSTRACT: The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.
    Full-text available · Article · Jan 2015 · Journal of Applied Physics
  • Lee A. Walsh · Greg Hughes · Conan Weiland · [...] · Chris Hobbs
    [Show abstract] [Hide abstract] ABSTRACT: The electrical, chemical, and structural interactions between Ni films and In0.53Ga0.47 As for source-drain applications in transistor structures have been investigated. It was found that for thick (> 10 nm) Ni films, a steady decrease in sheet resistance occurs with increasing anneal temperatures, however, this trend reverses at 450 degrees C for 5 nm thick Ni layers, primarily due to the agglomeration or phase separation of the Ni-(In,Ga) As layer. A combined hard-x-ray photoelectron spectroscopy (HAXPES) and x-ray absorption spectroscopy (XAS) analysis of the chemical structure of the Ni-(In,Ga)As alloy system shows: (1) that Ni readily interacts with In0.53Ga0.47 As upon deposition at room temperature resulting in significant interdiffusion and the formation of NiIn, NiGa, and NiAs alloys, and (2) the steady diffusion of Ga through the Ni layer with annealing, resulting in the formation of a Ga2O3 film at the surface. The need for the combined application of HAXPES and XAS measurements to fully determine chemical speciation and sample structure is highlighted and this approach is used to develop a structural and chemical compositional model of the Ni-(In,Ga)As system as it evolves over a thermal annealing range of 250 to 500 degrees C.
    Article · Dec 2014 · Physical Review Applied
  • Rinus TP Lee · Y Ohsawa · C Huffman · [...] · C Hobbs
    [Show abstract] [Hide abstract] ABSTRACT: ABSTRACT We report a record low contact resistivity of sub-1.0× 10-8 Ω. cm2 realized on n+ In0. 53Ga0. 47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to ..
    Conference Paper · Dec 2014
  • Rinus T.P. Lee · Y. Ohsawa · C. Huffman · [...] · C. Hobbs
    Conference Paper · Dec 2014
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    [Show abstract] [Hide abstract] ABSTRACT: Low-resistivity metal-semiconductor (M-S) contact is one of the urgent challenges in the research of 2D transition metal dichalcogenides (TMDs). Here, we report a chloride molecular doping technique which greatly reduces the contact resistance (Rc) in the few-layer WS2 and MoS2. After doping, the Rc of WS2 and MoS2 have been decreased to 0.7 kohm*um and 0.5 kohm*um, respectively. The significant reduction of the Rc is attributed to the achieved high electron doping density thus significant reduction of Schottky barrier width. As a proof-ofconcept, high-performance few-layer WS2 field-effect transistors (FETs) are demonstrated, exhibiting a high drain current of 380 uA/um, an on/off ratio of 4*106, and a peak field-effect mobility of 60 cm2/V*s. This doping technique provides a highly viable route to diminish the Rc in TMDs, paving the way for high-performance 2D nano-electronic devices.
    Full-text available · Article · Oct 2014 · Nano Letters
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    [Show abstract] [Hide abstract] ABSTRACT: In this paper, we report a novel chemical doping technique to reduce the contact resistance (Rc) of transition metal dichalcogenides (TMDs) - eliminating two major roadblocks (namely, doping and high Rc) towards demonstration of high-performance TMDs field-effect transistors (FETs). By using 1,2 dichloroethane (DCE) as the doping reagent, we demonstrate an active n-type doping density > 2*1019 cm-3 in a few-layer MoS2 film. This enabled us to reduce the Rc value to a record low number of 0.5 kohm*um, which is ~10x lower than the control sample without doping. The corresponding specific contact resistivity (pc) is found to decrease by two orders of magnitude. With such low Rc, we demonstrate 100 nm channel length (Lch) MoS2 FET with a drain current (Ids) of 460 uA/um at Vds = 1.6 V, which is twice the best value reported so far on MoS2 FETs.
    Full-text available · Conference Paper · Jun 2014
  • [Show abstract] [Hide abstract] ABSTRACT: Instability under positive bias stress in the InGaAs channel n-MOSFETs with gate last Al2O3 and gate-first ZrO2/Al2O3 process flows is investigated. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at the pre-existing defects located predominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the dielectric region adjacent to the substrate, while trap generation in the high-k bulk is negligible.
    Conference Paper · Jun 2014
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    [Show abstract] [Hide abstract] ABSTRACT: Growing good quality III–V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective way. In this paper, using physical analysis and electrical measurements of Esaki diodes, fabricated using molecular beam epitaxy grown ${rm In}_{0.53}{rm Ga}_{0.47}{rm As}$ layers on Si substrate, we show that the valley current density is strongly correlated with the underlying epi defect density. Such a strong correlation indicates that the valley characteristics can be used to monitor the epi quality. A model is proposed to explain the experimental observations and is validated using multiple temperature diode $I{-}V$ data. An excess defect density is introduced within the device using electrical and mechanical stress, both of which are found to have a direct impact on the valley current with a negligible change in the peak current characteristics, qualitatively supporting the model predictions.
    Full-text available · Article · Jun 2014 · IEEE Transactions on Electron Devices
  • C. D. Young · A. Neugroschel · K. Majumdar · [...] · C. Hobbs
    [Show abstract] [Hide abstract] ABSTRACT: Double-gate, fin-based Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers were subjected to bias temperature instability (BTI) evaluation where focus was placed on the crystallographic sidewall orientation and fin width dependence. For orientation dependence, BTI results at negative stress bias (NBTI) demonstrated that the (110) fin surface degraded more than the (100) surface, because more surface bonds are available in (110) to participate as bond-breaking trap centers during stress. For fin width dependence, positive BTI experienced no dependence on fin width; however, NBTI degradation increased as the fin width narrowed. A plausible cause is a concentration of electrons tunneled from the gate that reside in the SOI fin body. As the fin narrows, the sidewall device channel region moves in closer proximity to these concentrated electrons, which induces more band bending (i.e., increase the surface potential) at the fin/dielectricinterface resulting in a higher electric field and hole concentration in this region during stress, leading to more degradation.
    Conference Paper · Jun 2014
  • [Show abstract] [Hide abstract] ABSTRACT: We demonstrate a 300mm wafer scale conformal contact process to achieve uniform ultra-low specific contact resistivity (ρc) for metal/high-k/n+Si (MIS) contacts. To achieve conformal contacts, we use a sidewall TLM (STLM) test structure that helps to minimize current crowding effect and variability. A systematic study is provided by varying doping density (ND), high-k material (LaOx, ZrOx and TiOx) and high-k thickness (td) to optimize ρc. The obtained ρc and its uniformity are found to be comparable with standard nickel silicide technology, with a possibility of further improvement by use of lower work-function metal.
    Conference Paper · Jun 2014
  • [Show abstract] [Hide abstract] ABSTRACT: In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and interface trap(Dit) effects on electrostatic of III-V multi-gate(MG) nMOSFET which is critical to device scaling, we proposed a device design strategy for sub 7nm technology node.
    Conference Paper · Jun 2014
  • [Show abstract] [Hide abstract] ABSTRACT: Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl2O3/5nmZrO2 gate stack is studied. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔVT recovery impacts the degradation dependency on the stress duty cycle and frequency.
    Conference Paper · Apr 2014
  • T. Ngai · R. D. Clark · D. Veksler · [...] · P.D. Kirsch
    [Show abstract] [Hide abstract] ABSTRACT: In this paper, we provide a mechanistic understanding of mobility degradation of gate-last ZrO2 subjected to medium thermal budget annealing. We find that high-k post deposition anneal (PDA) even at modest temperatures can improve the interfacial layer (IL) and bulk oxide, but mobility suffers. The mechanism for this mobility degradation is the enhanced remote Coulomb scattering from nonstoichiometric ZrOx region near the IL. The high-k PDA, even at moderate temperature, enables oxygen gettering of the IL and deprives oxygen from ZrO2 near the IL, which results in the accumulation of defects/traps in the region near ZrO2/IL interface. This enhances remote Coulomb scattering due to the high concentration of oxide traps and their close proximity to the conductance channel. Consequently, mobility is degraded even though IL and bulk oxide are improved.
    Conference Paper · Apr 2014
  • [Show abstract] [Hide abstract] ABSTRACT: We report progress on surface passivation and functionalization of Ge channel surfaces, as well as high-k dielectric layer growth by atomic layer deposition (ALD) and the resulting electrical properties measured in transistor (MOSFET) and metal oxide semiconducting capacitor (MOSCAP) structures. Epitaxial Si and Al2O3 passivation of Ge show improved performance with 3 times reduction in interface states density (Dit), higher conductance, reduced hysteresis and sub-1nm EOT as opposed to non-passivated interface. A 3 times drive current improvement to Si MOSFET was achieved with thin Al2O3 passivation layer.
    Article · Mar 2014 · ECS Transactions
  • Kausik Majumdar · Chris Hobbs · P.D. Kirsch
    [Show abstract] [Hide abstract] ABSTRACT: In this letter, we propose a nonplanar transition metal dichalcogenide (TMD) channel field effect transistor and explore its ballistic performance in the ultimate scaling limit of sub-5 nm physical gate length (Lg) using self-consistent nonequilibrium Greens function framework. It is observed that electrostatic integrity remains intact even at such ultrashort Lg and physical scaling is eventually limited by direct source-drain tunneling. Benchmarking different TMD channels at various off-state current conditions shows potential for ultralow-leakage applications with small footprint, excellent energy efficiency, and moderate performance.
    Article · Feb 2014 · IEEE Electron Device Letters
  • [Show abstract] [Hide abstract] ABSTRACT: This paper reports tri-gate sub-100 nm In0.53Ga0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of gm, max > 1.5 mS/μm, at VDS = 0.5 V. This result is the best balance of gm, max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ0 = 760 cm2/V-s and peak vx0 = 1.6×107 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.
    Conference Paper · Dec 2013