[Show abstract][Hide abstract]ABSTRACT: A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria
[Show abstract][Hide abstract]ABSTRACT: The effect that surface modification of a nano-porous ultra-low k (p-ULK) dielectric film has upon Cu barrier layers has been investigated using a simulated RIE (reactive ion etching) process sequence. The specific surface conditions studied include post UV-cured, ash treated, and wet-etched by DHF (dilute HF), where these correspond to hydrophobic, hydrophilic, and hydrophobic wetting behavior, respectively. Blanket wafer substrates (300mm) were used to simulate wide-line features in integrated circuits. CVD was used to deposit p-ULK, in which the k-value is approximately 2.4. Two different Cu barrier stacks, PEALD-TaN/PVD-Ta and PVD-TaN/PVD-Ta, were deposited on the dielectrics following UV-cure/RIE surface modification. TEM studies indicate that the PEALD-TaN precursor did not show significant penetration into p-ULK film, even without pore-sealing. XRD measurements indicate that the PEALD-TaN underlayer promoted the formation the alpha-phase of PVD-Ta on top. Auger-Electron Spectroscopy (AES) analysis shows that the thickness and composition of the PEALD-TaN layer are independent of the surface conditions created by the UV/RIE processing. In conclusion, PEALD-TaN is comparable to PVD-TaN, with its excellent process stability originating from the plasma-enhanced deposition (promoting of the adsorption, bonding and densification of the precursor). PEALD processing can provide excellent step-coverage, uniformity and low-temperature deposition, at thicknesses less than those used for PVD. Thus PEALD-TaN is an excellent candidate as a Cu barrier for future nm-porous ULK integration.