Rong Zhao

Singapore University of Technology and Design, Singapore

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Publications (56)128.08 Total impact

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    Yi Tong · Xinyu Zhao · Mei Chee Tan · Rong Zhao
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    ABSTRACT: The advent of flexible optoelectronic devices has accelerated the development of semiconducting polymeric materials. We seek to replace conventional expensive semiconducting photodetector materials with our cost-effective composite system. We demonstrate in this work the successful fabrication of a photoconductive composite film of poly(3-hexylthiophene-2,5-diyl) (P3HT) mixed with NaYF4:Yb,Er nanophosphors that exhibited a ultrahigh photoresponse to infrared radiation. The high photocurrent measured was enabled by the unique upconversion properties of NaYF4:Yb,Er nanophosphors, where low photon energy infrared excitations are converted to high photon energy visible emissions that are later absorbed by P3HT. Here we report, a significant 1.10 × 10(5) times increment of photocurrent from our photoconductive composite film upon infrared light exposure, which indicates high optical-to-electrical conversion efficiency. Our reported work lays the groundwork for the future development of printable, portable flexible and functional photonic composites for light sensing and harvesting, photonic memory devices, and phototransistors.
    Full-text · Article · Nov 2015 · Scientific Reports
  • Kejie Huang · Rong Zhao · Yong Lian
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    ABSTRACT: A multicontext field-programmable gate array (FPGA) is a solution to achieve fast run-time reconfiguration. However, SRAM-based multicontext FPGAs still suffer from high leakage power during sleep, slow power-ON speed, and excessive large memory area. Racetrack memory is one of the most promising resistive nonvolatile memories, with the advantages of low power, high density, and high speed. In this paper, we propose two racetrack memory-based nonvolatile storage elements (NVSEs) for multicontext FPGAs. One is the shifting-based NVSE (type-1) with the advantages of high density and low power. The other one is the address-based NVSE (type-2) with the advantages of high context switching speed and low context switching power. The versatile place and route simulation results show that the type-1 NVSE-based eight-context FPGA reduces the area, critical path delay, and the power of the SRAM-based eight-context FPGA by more than 68.1%, 22.8%, and 13%, respectively. The proposed type-2 NVSE-based FPGAs allow the contexts to be switched 4.46 times faster than the type-1 NVSE-based FPGAs. Both designs improve the FPGA power-ON speed by more than a million times. Compared with the conventional racetrack memory-based lookup table (LUT), the proposed racetrack memory-based LUT may reduce the total power by more than 25%.
    No preview · Article · Sep 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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    ABSTRACT: The increasing demand for wearable electronic devices has made the development of highly elastic strain sensors that can monitor various physical parameters an essential factor for realizing next generation electronics. Here, we report an ultra-high stretchable and wearable device fabricated from dry-spun carbon nanotube (CNT) fibers. Stretching the highly oriented CNT fibers grown on a flexible substrate (Ecoflex) induces a constant decrease in the conductive path ways and contact areas between nanotubes depending on the stretching distance; this enables CNT fibers to behave as highly sensitive strain sensors. Owing to its unique structure and mechanism, this device can be stretched by over 900% while retaining high sensitivity, responsiveness, and durability. Furthermore, the device with biaxially oriented CNT fiber arrays shows independent cross-sensitivity, which facilitates simultaneous measurement of strains along multiple axes. We demonstrated potential applications of the proposed device, such as strain gauge, single and multi-axial detecting motion sensors. These devices can be incorporated into various motion detecting systems where their applications are limited to their strain.
    No preview · Article · Jun 2015 · ACS Nano
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    ABSTRACT: Increase in conductivity and mechanical properties of a carbon nanotube (CNT) fiber inspired by mussel-adhesion chemistry is described. Infiltration of polydopamine into an as-drawn CNT fiber followed by pyrolysis results in a direct insulation-to-conduction transformation of poly(dopamine) into pyrolyzed-poly(dopamine) (py-PDA), retaining the intrinsic adhesive function of catecholamine. The py-PDA enhances both the electrical conductivity and the mechanical strength of CNT fibers. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
    Full-text · Article · Apr 2015 · Advanced Materials
  • Kejie Huang · Rong Zhao · Yong Lian
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    ABSTRACT: The continuing miniaturization of complementary metal oxide semiconductor (CMOS) technology has brought in two critical issues—the high power and long global interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents a new design of the key component in processors—multi-bit full adder, whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RTM). The MTJ sharing technique with demultiplexing approach is used in the proposed non-volatile full adder (NVFA) to greatly reduce the area and power, and improve the speed and sensing margin as well. The proposed NVFA scheme can also apply to the other types of non-volatile memory (NVM). Compared to the state-of-art magnetic full adder (MFA), our proposed NVFA has reduced the power and area by 5.9 times and 50%, respectively. It also accelerates the speed by 10% and increases the sensing margin by more than 66%.
    No preview · Article · Apr 2015 · Circuits and Systems I: Regular Papers, IEEE Transactions on
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    Full-text · Article · Jan 2015 · International Journal of Intelligence Science
  • Kejie Huang · Rong Zhao · Wei He · Yong Lian
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    ABSTRACT: The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.
    No preview · Article · Jan 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Kejie Huang · Rong Zhao
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    ABSTRACT: The computing systems are scaling down 100 times every decade, while the processing power doubles every two years. As a result, the power density has been the one of the most critical issues that limit the modern processors. Therefore, new technologies and computer architectures are under tensed development to reduce the power consumption. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power issue. Meanwhile, it could be stacked on top of CMOS circuits to break the bottleneck of memory bandwidth limitation. This paper presents new designs of the non-volatile logic gates, which are compared with the conventional designs including non-volatile flip-flops, fully non-volatile logic gates, and hybrid non-volatile logic gates. The simulation results show that proposed non-volatile logic gates have the advantage of low power, especially at the low switching frequency. The proposed XOR has reduced the power consumption of XOR in the conventional load/save systems by 45% at high switching frequency, and 92% at 100 kHz. The proposed designs also show the advantage of reconfigurability, which makes the designs more flexible and robust.
    No preview · Conference Paper · Oct 2014
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    ABSTRACT: Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (similar to 33% to similar to 55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds. (C) 2014 AIP Publishing LLC.
    No preview · Article · Oct 2014 · Applied Physics Letters
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    ABSTRACT: The ultrahigh demand for faster computers is currently tackled by traditional methods such as size scaling (for increasing the number of devices), but this is rapidly becoming almost impossible, due to physical and lithographic limitations. To boost the speed of computers without increasing the number of logic devices, one of the most feasible solutions is to increase the number of operations performed by a device, which is largely impossible to achieve using current silicon-based logic devices. Multiple operations in phase-change-based logic devices have been achieved using crystallization; however, they can achieve mostly speeds of several hundreds of nanoseconds. A difficulty also arises from the trade-off between the speed of crystallization and long-term stability of the amorphous phase. We here instead control the process of melting through premelting disordering effects, while maintaining the superior advantage of phase-change-based logic devices over silicon-based logic devices. A melting speed of just 900 ps was achieved to perform multiple Boolean algebraic operations (e.g., NOR and NOT). Ab initio molecular-dynamics simulations and in situ electrical characterization revealed the origin (i.e., bond buckling of atoms) and kinetics (e.g., discontinuouslike behavior) of melting through premelting disordering, which were key to increasing the melting speeds. By a subtle investigation of the well-characterized phase-transition behavior, this simple method provides an elegant solution to boost significantly the speed of phase-change-based in-memory logic devices, thus paving the way for achieving computers that can perform computations approaching terahertz processing rates.
    Full-text · Article · Sep 2014 · Proceedings of the National Academy of Sciences
  • Kejie Huang · Rong Zhao · Yong Lian
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    ABSTRACT: The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.
    No preview · Conference Paper · Jul 2014
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    ABSTRACT: Learning scheme is the key to the utilization of spike-based computation and the emulation of neural/synaptic behaviors toward realization of cognition. The biological observations reveal an integrated spike time- and spike rate-dependent plasticity as a function of presynaptic firing frequency. However, this integrated rate-temporal learning scheme has not been realized on any nano devices. In this paper, such scheme is successfully demonstrated on a memristor. Great robustness against the spiking rate fluctuation is achieved by waveform engineering with the aid of good analog properties exhibited by the iron oxide-based memristor. The spike-time-dependence plasticity (STDP) occurs at moderate presynaptic firing frequencies and spike-rate-dependence plasticity (SRDP) dominates other regions. This demonstration provides a novel approach in neural coding implementation, which facilitates the development of bio-inspired computing systems.
    Full-text · Article · Apr 2014 · Scientific Reports
  • Kejie Huang · Rong Zhao · Ning Ning · Yong Lian
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    ABSTRACT: The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but still face the challenges of high saving power and area overhead, and low data reliability. This paper presents a new resistive Non-Volatile Memory (NVM) based circuit architecture with zero leakage power dissipation. It stores the states of the registers in the localized spin-torquetransfer magnetic random access memory (STT-MRAM) array through scan chains, which has reduced by more than 20% sleep energy than conventional nvFF schemes, and saved by more than 99:8% sleep energy compared to the retention CMOS register based approaches when the sleep time is longer than 1s. Moreover, the proposed pipelined quad-phase saving scheme maximizes the saving speed, while reduces the peak saving current.
    No preview · Article · Apr 2014 · Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Kejie Huang · Yajun Ha · Rong Zhao · Akash Kuma · Yong Lian
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    ABSTRACT: The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high resistance ratio. However, most of the reported PCM-based FPGAs have significant active leakage power and reliability issues. This paper presents a low active leakage power and high reliability PCM based non-volatile SRAM (nvSRAM). The low active leakage power and high reliability are achieved by biasing PCM cells at 0 V during FPGA operation. Compared to the state-of-the-art, the proposed nvSRAM based 4-input look up table (LUT) achieves 174 times reduction in active leakage power and 15000 times increase in retention time. In addition, the proposed nvSRAM-based FPGA system significantly accelerates the loading speed to less than 1 ns with 2.54 fJ/cell loading energy.
    No preview · Article · Mar 2014 · Circuits and Systems I: Regular Papers, IEEE Transactions on
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    ABSTRACT: A compositionally matched superlattice-like (SLL) structure comprised of Ge2Sb2Te5 (GST) and nitrogen-doped GST (N-GST) was developed to achieve both low current and high endurance Phase Change Random Access Memory (PCRAM). N-GST/GST SLL PCRAM devices demonstrated ∼37% current reduction compared to single layered GST PCRAM and significantly higher write/erase endurances of ∼108 compared to ∼106 for GeTe/Sb2Te3 SLL devices. The improvements in endurance are attributed to the compositionally matched N-GST/GST material combination that lowers the diffusion gradient between the layers and the lower crystallization-induced stress in the SLL as revealed by micro-cantilever stress measurements.
    No preview · Article · Sep 2013 · Applied Physics Letters
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    ABSTRACT: Significant improvements in the spatial and temporal uniformities of device switching parameters are successfully demonstrated in Ge/TaOx bilayer-based resistive switching devices, as compared with non-Ge devices. In addition, the reported Ge/TaOx devices also show significant reductions in the operation voltages. Influence of the Ge layer on the resistive switching of TaOx-based resistive random access memory is investigated by X-ray spectroscopy and the theory of Gibbs free energy. Higher uniformity is attributed to the confinement of the filamentary switching process. The presence of a larger number of interface traps, which will create a beneficial electric field to facilitate the drift of oxygen vacancies, is believed to be responsible for the lower operation voltages in the Ge/TaOx devices.
    Full-text · Article · Sep 2013 · IEEE Electron Device Letters
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    Kejie Huang · Rong Zhao
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    ABSTRACT: A writing circuit for a resistive memory cell arrangement is provided, the resistive memory cell arrangement including a plurality of resistive memory cells. The writing circuit includes a controlled voltage source including a plurality of pass transistors, wherein each pass transistor includes a first source/drain terminal, a second source/drain terminal and a gate terminal, and wherein the first source/drain terminal is configured to be electrically coupled to a power supply line and the second source/drain terminal is configured to be electrically coupled to a bit line associated with a resistive memory cell of the plurality of resistive memory cells, and a plurality of switches, wherein each switch is configured to control the gate terminal of the pass transistor, wherein the controlled voltage source is configured to supply a voltage to the resistive memory cell for a write operation. Further embodiments provide a resistive memory cell arrangement.
    Full-text · Patent · Sep 2012
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    ABSTRACT: TiWOx interfacial layer was proposed and implemented to act as both heater and inter-diffusion barrier for phase change memory through a complementary metal-oxide semiconductor compatible oxidization process. Significant reduction of RESET current was obtained due to more efficient Joule heating and better thermal confinement. About one order of magnitude endurance increase was achieved for the device with TiWOx due to suppression of inter-diffusion between Ge2Sb2Te5 and TiW. The change of the minimum RESET voltage against cycling was reduced by TiWOx layer with shorter RESET pulse, which would benefit device cyclability.
    No preview · Article · Aug 2012 · Applied Physics Letters
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    ABSTRACT: Thermal stability of 100 nm Ge2Sb2Te5 thin film during annealing from room temperature to 240 °C inside a UHV chamber was studied in situ by X-ray photoelectron spectroscopy (XPS) and ex situ by X-ray diffraction (XRD) and atomic force microscopy (AFM). Ge species are found to diffuse preferentially to the surface when GST film is annealed from 25 °C to 100 °C. This process is accompanied by a change of phase whereby the amorphous film completely becomes face-center-cubic (FCC) phase at 100 °C. From 100 °C to 200 °C, both Sb and Te species are observed to diffuse more to the surface. The FCC phase is partially changed into hexagonal-close-pack (HCP) phase at 200 °C. At 220 °C, FCC phase is completely transformed into HCP phase. Loss of Sb and Te are also detected from the surface and this is attributed to desorption due to their high vapor pressures. At 240 °C, Sb and Te species are found to have desorbed completely from the surface, and leave behind Ge-rich 3D droplets on the surface. The separation of Ge2Sb2Te5 into Sb,Te-rich phase and Ge-rich phase is thus the main mechanism to account for the failure of Ge2Sb2Te5-based phase change memory devices under thermal stress.
    Full-text · Article · Jun 2012 · Applied Surface Science
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    ABSTRACT: The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory.
    Full-text · Article · Apr 2012 · Scientific Reports