Arijit Raychowdhury

Georgia Institute of Technology, Atlanta, Georgia, United States

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Publications (112)77.72 Total impact

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    Full-text · Article · Jan 2016
  • Saad Nasir · Samantak Gangopadhyay · Arijit Raychowdhury

    No preview · Article · Jan 2016 · IEEE Transactions on Power Electronics
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    Paolo Maffezzoni · Luca Daniel · Nikhil Shukla · Suman Datta · Arijit Raychowdhury
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    ABSTRACT: This paper deals with modeling and simulation of a new family of two-terminal devices fabricated with vanadium dioxide material. Such devices allow realization of very compact relaxation nano-oscillators that can be connected electronically to form arrays of coupled oscillators. Challenging applications of oscillator arrays include the realization of multiphase signal generators and massively parallel brain-inspired neurocomputing. In the paper, a circuit-level model of the vanadium dioxide device is provided which enables extensive electrical simulations of oscillator systems built on the device. The proposed model is exploited to explain the dynamics of vanadium dioxide relaxation oscillators as well as to accomplish a robust parameter design. Applications to the realization of voltage-controlled oscillators and of multiphase oscillator arrays are illustrated.
    Preview · Article · Sep 2015 · Circuits and Systems I: Regular Papers, IEEE Transactions on
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    Samantak Gangopadhyay · Saad Bin Nasir · Arijit Raychowdhury
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    ABSTRACT: By the year 2020 it is expected that corresponding to every human being there would be seven connected devices. These connected devices will usher in the Internet of Things (IoTs) and would percolate every aspect of human life, changing the human experience at a fundamental level. In order to power these devices novel strategies would have to be developed as these devices will not only have a dynamic load, due to multIPle features, but also dynamic sources if opportunistic energy harvesting is used to supplement the rechargeable battery. For the power delivery network, figures of merit would be to comprehend both the ability to supply the worst case design as well as to maintain high efficiency across a wide dynamic range. To maintain high efficiency for a large range we will need adaptive components on the load side as well as at the energy source. In this work we will discuss the general IoT power delivery network (PDN), current research and the state of the art PDN components, novel designs and control for interface circuits and energy harvesters.
    Full-text · Dataset · Aug 2015
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    Inna Vaisband · Saad Bin Nasir · Arijit Raychowdhury
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    ABSTRACT: Increasing level of transistor integration with multiple voltage domains and power states, ever decreasing decoupling capacitance, fast load transients and the need for fine-grained spatio-temporal power management provide impetus for embedding distributed point of load (PoL) linear regulators deep within digital functional blocks of microprocessors and Systems-on-Chip (SoCs). This demands modularity in design as well as process and voltage scalability of such linear regulators. Digital linear regulators have emerged as an attractive counterpart to the traditional analog solutions. This paper presents the circuit implementation and a steady state response model of a discrete-time digital regulator with simulations and hardware measurements with an emphasis on the steady state oscillations. We develop parametric models to demonstrate design trade-offs for a stable steady state response.
    Full-text · Dataset · Aug 2015
  • P. Maffezzoni · L. Daniel · N. Shukla · S. Datta · A. Raychowdhury · V. Narayanan
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    ABSTRACT: An original circuit-level model of two-terminal vanadium dioxide electron devices exhibiting electronic hysteresis is presented. Such devices allow realisation of very compact relaxation nano-oscillators that potentially can be used in bio-inspired neurocomputing. The proposed model is exploited to determine the parameters, values that ensure stable periodic oscillations.
    No preview · Article · May 2015 · Electronics Letters
  • S.B. Nasir · S. Gangopadhyay · A. Raychowdhury
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    ABSTRACT: An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and ultra-wide current dynamic range of digital load circuits (for low power on one end while maintaining performance at another) necessitate the design of high-efficiency, compact on-die voltage regulators providing ultra-fine grained spatio-temporal voltage distribution [1,2]. Digitally implementable linear regulators operated in low-dropout (LDO) mode, based on continuous time or discrete time control, exhibit process and voltage scalability [3-5], thus supplementing their analog counterparts [6].
    No preview · Article · Mar 2015
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    ABSTRACT: Information processing applications related to associative computing like image / pattern recognition consume excessive computational resources in the Boolean processing framework. This motivates the exploration of a non-Boolean computing approach for such applications. In this work, we demonstrate, (i) novel hybrid set of pair-wise coupled oscillators comprising of vanadium dioxide (VO2) metal-insulator-transition (MIT) system integrated with MOSFET; (ii) degree of synchronization between oscillators based on input analog voltage difference; (iii) implementation of hardware platform for fast and efficient evaluation of Lk fractional distance norm (k<1); (iv) improved quality of image processing and ∼20X lower power consumption of the coupled oscillators over a CMOS accelerator.
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
  • A. Raychowdhury · S.B. Nasir · S. Gangopadhyay
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    ABSTRACT: Variations, both static and dynamic in nature, impact the performance and power-efficiency of microprocessors and other digital integrated circuits. While static process variations can often be mitigated through binning or by post-silicon tuning, dynamic variations change as a function of time and environment and cannot be reduced by static tuning. Examples of these types of dynamic variations include power supply (VCC) droop, temperature change, and device aging over time. The droop magnitude, frequency and duration depend on the complex interaction of capacitive and inductive parasitics at the board, package, and die levels and change with the workload and current demand [1-3]. VCC droops contain high-frequency (i.e., fast changing) and low-frequency (i.e., slow changing) components and occur locally and/or globally across the die. Temperature variations occur at a relatively slower time scale with local hot spots on the die, depending on environmental and workload conditions as well as the heat-removal capability of the package. Further, transistor aging slowly degrades the drive current over time as a function of gate bias and temperature conditions. Conventional designs build in VCC guardband (VCC GB) at a target frequency to ensure correct functionality even in the presence of worst-case dynamic variations. In the digital core, this GB accounts for the delay increase on critical paths when dynamic variations occur and guarantees that timing constraints are met even under worst-case conditions. In the storage arrays (register files and caches) this GB is added to the static minimum operating voltage (VMIN) to obtain the resultant operating VMIN and results in an increase of both leakage and dynamic array power. The key design aspect of adaptive and resilient designs is to remove a part of this GB, such that logic timing and memory functionality can be met at a lower VCC. This improves energy efficiency and improves battery life; a key consideration in mobile and handheld platforms. The mitigation of the design GB can be achieved in two fundamentally different ways. For dynamic variations with time scales in the order of hundreds of μs to ms (such as temperature variations or transistor aging), a reactive scheme where any functional error is avoided is applicable. For example, embedded temperature sensors can be used to trigger changes in the clock frequency or changes in the supply voltage, such that at low temperatures (when transistor currents are higher) a faster clock (at iso-VCC) or a lower supply (at iso-clock frequency) can be employed [4]. For dynamic changes which occur in time scales of ns to μs, such reactive schemes are impossible by design. Hence, an alternative scheme can be employed where timing errors (in logic) or read-write errors (in memory) are allowed to happen. Once errors occur, they are detected, and the errant instruction is replayed with proper care such that data integrity is maintained. A combination of such adaptive schemes (Fig. 1) result in the mitigation of a major part of the design GB, resulting in higher energy efficiency.
    No preview · Article · Jan 2015
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    Saad Bin Nasir · Arijit Raychowdhury
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    ABSTRACT: With an increasing number of power-states, finer- grained power management and larger dynamic ranges of digital circuits, the integration of compact, scalable linear-regulators embedded deep within logic blocks has become important. While analog linear-regulators have traditionally been used in digital ICs, the need for digitally implementable designs that can be synthesized and embedded in digital functional units for ultra fine- grained power management has emerged. This paper presents the circuit design and control models of an all-digital, discrete-time linear regulator and explores the parametric design space for transient response time and loop stability.
    Preview · Article · Jan 2015

  • No preview · Article · Jan 2015 · IEEE Transactions on Computers
  • Abhinav Parihar · Nikhil Shukla · Suman Datta · Arijit Raychowdhury
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    ABSTRACT: As complementary metal-oxide-semiconductor (CMOS) scaling continues to offer insurmountable challenges, questions about the performance capabilities of Boolean, digital machine based on Von-Neumann architecture, when operated within a power budget, have also surfaced. Research has started in earnest to identify alternative computing paradigms that provide orders of magnitude improvement in power-performance for specific tasks such as graph traversal, image recognition, template matching, and so on. Further, post-CMOS device technologies have emerged that realize computing elements which are neither CMOS replacements nor suited to work as a binary switch. In this paper, we present the realization of coupled and scalable relaxation-oscillators utilizing the metal-insulator-metal transition of vanadium-dioxide (VO2) thin films. We demonstrate the potential use of such a system in a non-Boolean computing paradigm and demonstrate pattern recognition, as one possible application using such a system.
    No preview · Article · Dec 2014 · IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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    ABSTRACT: The need for fine-grained power management in digital ICs has led to the design and implementation of compact, scalable low-drop out regulators (LDOs) embedded deep within logic blocks. While analog LDOs have traditionally been used in digital ICs, the need for digitally implementable LDOs embedded in digital functional units for ultrafine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control model of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current efficiency of 98%.
    No preview · Article · Nov 2014 · IEEE Journal of Solid-State Circuits
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    Abhinav Parihar · Nikhil Shukla · Suman Datta · Arijit Raychowdhury
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    ABSTRACT: Computing with networks of synchronous oscillators has attracted wide-spread attention as novel materials and device topologies have enabled realization of compact, scalable and low-power coupled oscillatory systems. Of particular interest are compact and low-power relaxation oscillators that have been recently demonstrated using MIT (metal-insulator-transition) devices using properties of correlated oxides. Further the computational capability of pairwise coupled relaxation oscillators has also been shown to outperform traditional Boolean digital logic circuits. This paper presents an analysis of the dynamics and synchronization of a system of two such identical coupled relaxation oscillators implemented with MIT devices. We focus on two implementations of the oscillator: (a) a D-D configuration where complementary MIT devices (D) are connected in series to provide oscillations and (b) a D-R configuration where it is composed of a resistor (R) in series with a voltage-triggered state changing MIT device (D). The MIT device acts like a hysteresis resistor with different resistances in the two different states. The synchronization dynamics of such a system has been analyzed with purely charge based coupling using a resistive (RC ) and a capacitive (CC ) element in parallel. It is shown that in a D-D configuration symmetric, identical and capacitively coupled relaxation oscillator system synchronizes to an anti-phase locking state, whereas when coupled resistively the system locks in phase. Further, we demonstrate that for certain range of values of RC and CC , a bistable system is possible which can have potential applications in associative computing. In D-R configuration, we demonstrate the existence of rich dynamics including non-monotonic flows and complex phase relationship governed by the ratios of the coupling impedance. Finally, the developed theoretical formulations have been shown to explain experimentally measured waveforms of such pairwise coupled relaxation oscillators.
    Preview · Article · Aug 2014 · Journal of Applied Physics
  • Suman Datta · Nikhil Shukla · Matthew Cotter · Abhinav Parihar · Arijit Raychowdhury
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    ABSTRACT: Harnessing the computational capabilities of dynamical systems has attracted the attention of scientists and engineers form varied technical disciplines over decades. The time evolution of coupled, non-linear synchronous oscillatory systems has led to active research in understanding their dynamical properties and exploring their applications in brain-inspired, neuromorphic computational models. In this paper we present the realization of coupled and scalable relaxation-oscillators utilizing the metal-insulator-metal transition of vanadium-dioxide (VO2) thin films. We demonstrate the potential use of such a system in pattern recognition, as one possible computational model using such a system.
    No preview · Article · Jun 2014
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    ABSTRACT: Strongly correlated phases exhibit collective carrier dynamics that if properly harnessed can enable novel functionalities and applications. In this article, we investigate the phenomenon of electrical oscillations in a prototypical MIT system, vanadium dioxide (VO2). We show that the key to such oscillatory behaviour is the ability to induce and stabilize a non-hysteretic and spontaneously reversible phase transition using a negative feedback mechanism. Further, we investigate the synchronization and coupling dynamics of such VO2 based relaxation oscillators and show, via experiment and simulation, that this coupled oscillator system exhibits rich non-linear dynamics including charge oscillations that are synchronized in both frequency and phase. Our approach of harnessing a non-hysteretic reversible phase transition region is applicable to other correlated systems exhibiting metal-insulator transitions and can be a potential candidate for oscillator based non-Boolean computing.
    Full-text · Article · May 2014 · Scientific Reports
  • Saad Bin Nasir · Youngtak Lee · Arijit Raychowdhury
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    ABSTRACT: On-chip power delivery networks (PDNs) for today's microprocessors and systems-on-chip (SoCs), which are characterized by dynamic supply voltage, many embedded integrated VRs (IVRs), lower decoupling-capacitor, high current ranges, multiple power modes and fast transient loads are designed to minimize AC load transients and supply noise. The close interaction of the VRs with the power grids create multiple feedback paths in the overall network, compromising the resultant phase margin and can even lead to system instabilities. The introduction of digital linear regulators operating in the low dropout (LDO) mode, with low power supply rejection, further exacerbates the problem. This paper provides a comprehensive methodology, based on Mason's Gain Formula applied to hybrid control, for modeling and analyzing distributed linear regulators and their interaction with the PDN.
    No preview · Conference Paper · Mar 2014
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    ABSTRACT: In this paper, we present a low-power graphics processing core that achieves a 40% improvement in peak energy efficiency using dual-VCC arrays, adaptive clocking for voltage droop mitigation, and state retention capability with an integrated retention clamping circuit for low-power sleep mode. The 22nm testchip includes a graphics execution core connected to an SRAM array and test controller used for storage and delivery of at-speed test vectors. Correct execution of the tests is validated through a multiple-input signature register (MISR), which accumulates key signals in the core and generates a 32b signature at test completion.
    No preview · Conference Paper · Feb 2014
  • Samantak Gangopadhyay · Youngtak Lee · Saad Bin Nasir · Arijit Raychowdhury
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    ABSTRACT: Discrete time digital linear regulators, including low dropout regulators (LDOs) have become competitive in muti-Vcc digital systems for fine-grained spatio-temporal voltage regulation and distribution. However, wide dynamic current range of the digital load circuits poses serious problems in maintaining stability and high efficiency at all corners. In this paper we present a control model for discrete time LDOs and demonstrate how online adaptive control can be employed for consistent performance and high efficiency across the load current range.
    No preview · Conference Paper · Jan 2014
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    ABSTRACT: Advanced human-machine interfaces require improved embedded sensors that can seamlessly interact with the user. Voice-based communication has emerged as a promising interface for next generation mobile, automotive and hands-free devices. Presented here is such an audio front-end with Voice Activity Detection (VAD) hardware targeted for low-power embedded SoCs, featuring a 512 pt FFT, programmable filters, noise floor estimator and a decision engine which has been fabricated in 32 nm CMOS. The dual-VCC, dual-frequency design allows the core datapath to scale to near-threshold voltage (NTV), where power consumption is less than 50 uW. At peak energy efficiency, the core can process audio data at 2.3 nJ/frame - a 9.4X improvement over nominal voltage conditions.
    No preview · Article · Aug 2013 · IEEE Journal of Solid-State Circuits

Publication Stats

2k Citations
77.72 Total Impact Points


  • 2010-2015
    • Georgia Institute of Technology
      • School of Electrical & Computer Engineering
      Atlanta, Georgia, United States
  • 2009-2014
    • Intel
      • Intel IT Labs
      Santa Clara, California, United States
  • 2003-2009
    • Purdue University
      • School of Electrical and Computer Engineering
      West Lafayette, IN, United States