[Show abstract][Hide abstract] ABSTRACT: This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.
[Show abstract][Hide abstract] ABSTRACT: The high-speed and high-resolution ADC is a key enabler for many future wireless communications systems. The digital background calibration technique can be used to reduce the total power consumption by enhancing the linearity without using high-gain amplifiers. One of the main practical constraints in the wireless applications is a short time available for calibration. This paper proposes a novel fast calibration method of pipelined ADCs, suitable for wireless communications applications, where a sufficiently high resolution can be achieved without requiring any calibration period.