[Show abstract][Hide abstract] ABSTRACT: SOC design has became prevalent implementation approach of GNSS receiver, while software/hardware partition of the chip has directly impact its performance and cost. It is analyzed that the undirected graphs theory is applied in the software/hardware partition in the paper. And a partition algorithm is demonstrated. The optimal partitioning method is generally described as 2 problems. The presented method obtains the solution for Problem 1 by choosing the optimum in Problem 2's solution space. The method's computation speed is optimized in the use of two-phrase search to gradually decrease the search range. Compared with using the heuristic algorithm, the computation complexity is reduced from O(n3) to O(Anlogn). Experimental results show that the proposed algorithm's solution is the same with other common method, while in the terms of computation speed the algorithm is 70% faster than GA, and 20%–30% faster than KL in the case of large vertices.
[Show abstract][Hide abstract] ABSTRACT: With the rapid increases of signal frequency and reduction of feature sizes of high-speed electronic circuits in modern VLSI design, it is becoming more and more important to design and optimize power/ground networks fast and efficiently. A method for the design of the power/ground networks at the floor-planning stage is presented, which calculates the number of pads and straps and width of straps first, and then optimizes the power/ground networks considering the Macro's power consumption. Experimental results based on the digital television transmitter modulator design show that final IR drop is within the required range and the method is efficient and reliable.
[Show abstract][Hide abstract] ABSTRACT: The verification takes over 70% of the whole workload in design of digital chips, especially the chips for communications. Practically, the FPGA verification is common used because the simulation verification is low-efficient. But it is not a perfect substitute for the simulation verification. So the method to improve the efficiency of the simulation should be investigated. The verification system proposed in this paper has been used in the verification work of the chips of the Dual-system navigation receiverpsilas baseband circuit. The verification methods in the system reduce the debug time, which are separating the part of the verification process to avoid the repetition and providing the real-time interactive interface to the designer.