- [Show abstract] [Hide abstract] ABSTRACT: In this letter, we propose a layer selection method by permutations (LSMPs) of string select line (SSL) bias and string select transistor with multi-level states. Due to the increased number of threshold voltage orderings by the permutation, the number of required SSLs for the layer selection and the space occupied by SSLs can be minimized. Also, the operation scheme for the layer selection is discussed. To verify the operation of proposed LSMP, a fabricated pseudo-LSM is measured. As a result, it is clearly revealed that the number of selectable layer can be increased drastically by the LSMP.
- [Show abstract] [Hide abstract] ABSTRACT: A comprehensive study was done regarding stability under simultaneous stress of light and negative gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors. A negative threshold voltage (Vth) shift and an anomalous hump were observed in transfer characteristics after the stress, and it is explained that these phenomena are caused by the hole trapping in the SiO2 gate insulator, not by interface state generation. Furthermore, capacitance-voltage (CG-VG) measurements were performed with various frequencies to investigate the vertical distribution of the trapped holes in the gate insulator. As a result, the correlation between the vertical location of the trapped holes and the influence on CG-VG characteristics were revealed clearly. First, at the beginning of the stress, photogenerated holes are mainly trapped at the α-HIZO/SiO2 interface and interfacial SiO2 in contact with the interface, which induces the negative Vth shift. Second, as the stress time increases, the holes start to be trapped in the spatially deeper insulator, which leads to an additional hump in the CG-VG characteristics at sufficiently low frequencies.
Dataset: 201205IEICE E95-C 5 837
- [Show abstract] [Hide abstract] ABSTRACT: Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.
- [Show abstract] [Hide abstract] ABSTRACT: In this letter, we propose a simplified channel stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (Vth) setting method that all the SSTs on each layer are set to targeted the Vth values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the Vth values of SSTs are set to the targeted Vth values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the Vth values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.
- [Show abstract] [Hide abstract] ABSTRACT: A charge trap flash (CTF) memory cell consists of oxide-nitride-oxide multilayer dielectrics and the electron/hole trapping within the silicon nitride layer is the main charge storage mechanism for program/erase operation. However, CTF memory cells have some technical issues, such as the electron back-tunneling phenomenon which causes the non-fully erased state and makes its memory window narrow and memory speed slow during erase operation. In this paper, we focus on the effects of the blocking oxide energy barrier from the control gate on the memory characteristics in CTF memory cells. Our experimental results show that a relatively high gate/blocking oxide energy barrier leads to a reduced non-fully erased state problem but a smaller program threshold voltage shift; conversely, a relatively low gate/blocking oxide energy barrier leads to a larger program threshold voltage shift but a significant non-fully erased state problem. All of these results will contribute to understand the trade-offs between the gate/blocking oxide energy barrier and memory window for optimizing CTF memory cell performance.
- [Show abstract] [Hide abstract] ABSTRACT: In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.
- [Show abstract] [Hide abstract] ABSTRACT: In this study, the gate-all-around (GAA) poly-Si channel flash memories with a nitride charge trap layer (Si<sub align="right"> 3 </sub>N<sub align="right"> 4 </sub>) have been successfully fabricated. Electrical characteristics of fabricated devices including the threshold voltage shift with program/erase operation have been investigated. Gate structures were formed differently according to each defined channel width. Results show that devices with the gate-all-around structure have superior program efficiency. To investigate the effect of gate structure on the program efficiency, TCAD simulation was carried out. Another issue of the fabricated devices is poor erase operation due to the quality of the blocking oxide. This issue has been studied through the capacitor composed of the same stack structure, and the way to improve the erase operation has been proposed.
- [Show abstract] [Hide abstract] ABSTRACT: In this study, the characteristics of the nitride-based blue light emitting diodes (LEDs) having different indium contents multiple quantum barriers were analyzed numerically. The carrier concentrations in the quantum wells (QWs), energy band diagrams, radiative recombinations were investigated. InxGa1-xN with different indium-composition multiple quantum barriers (QBs) instead of GaN QBs were designed to improve hole transport and radiative recombination. The simulation results indicate that LEDs have a better hole transport in the active regions and uniformity of hole concentration over the conventional LED with GaN QBs. Consequently, the luminescence power of proposed structure was enhanced about 60 times at 3.0 V. (c) 2013 The Japan Society of Applied Physics
- [Show abstract] [Hide abstract] ABSTRACT: In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.
- [Show abstract] [Hide abstract] ABSTRACT: In this study, we investigate the variation of threshold voltage and ON-cell current caused by cell gate length fluctuation in silicon--oxide--nitride--oxide--silicon (SONOS) NAND flash memory with virtual source and drain (VSD). The fluctuation in cell gate length caused by process errors such as line edge roughness, etch slope variation, and lithography resolution-induced error affects threshold voltage and ON-cell current considerably. Our results show that three-dimensional (3D) structures have robust immunity to the cell gate length fluctuation effect. From the viewpoint of array design, threshold voltage and ON-cell current variation due to cell gate length fluctuation can be reasonably mitigated by enlarging the cell gate length in a word line (WL) pitch and reducing the body doping concentration. In addition, the tendency of the variation by technology node scaling and the comparison with the junctionless NAND flash memory structure are also investigated.
- [Show abstract] [Hide abstract] ABSTRACT: In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).
- [Show abstract] [Hide abstract] ABSTRACT: We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) . Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.
- [Show abstract] [Hide abstract] ABSTRACT: A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F$^2$ size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.
- [Show abstract] [Hide abstract] ABSTRACT: Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.
- [Show abstract] [Hide abstract] ABSTRACT: Supply voltage (VDD) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1-2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported . Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO2 in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.
- [Show abstract] [Hide abstract] ABSTRACT: Modern VLSI technology has been developed with continuous scaling of MOSFET. However, as MOSFET has been scaled down, a lot of critical issues have risen and resulted in a considerable degradation of individual devices . On the other hand, owing to its periodic on/off characteristic, single-electron transistor (SET) attracts attention with its promising performance. But, in general, fabricating SET, silicon-on-insulator (SOI) wafers have been used for their leakage current through buried oxide (BOX) on the substrate region . However, in this paper, we propose a vertical structure that is fabricated on a bare wafer, not on a SOI wafer, and the fabrication process with which small size of a quantum dot (QD) can be formed more easily than previous works . Since the smaller QD a SET has, the better operation characteristic it has at room temperature (RT), the characteristic of the SET device can be observed more clearly than previous works with the simple process to downsize a QD.
- [Show abstract] [Hide abstract] ABSTRACT: As the needs for high density NAND flash memory have been dramatically increasing, the memory density has also increased by scaling down the technology node. As the scaling of NAND flash memory is accelerated, the short channel effect is more severe and further scaling down is faced with process limitations. So, various types of 3D stacked NAND flash memory has been introduced and reported for ultra-high-density data storage and Fig. 1 shows one of the previously reported 3D stacked NAND flash memory structures [1–3]. However, as the distance between layers is reduced, several channel coupling problems are emerging. In this paper, we investigate the self boosting disturbance induced by channel coupling between layers in the 3D stacked NAND flash memory.
- [Show abstract] [Hide abstract] ABSTRACT: Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type -. However, theses structures have several drawbacks. For TCAT, declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different elecric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT, it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).
- [Show abstract] [Hide abstract] ABSTRACT: For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (V<sub>th</sub>) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO<sub>2</sub> at the edge regions along the channel length/width directions and that a negative V<sub>th</sub> shift is derived from hole trapping in the gate insulator far from the SiO<sub>2</sub>/HIZO interface.
Seoul National University
Sŏul, Seoul, South Korea
- School of Electrical Engineering and Computer Sciences