[Show abstract][Hide abstract] ABSTRACT: A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.
No preview · Article · Oct 2010 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.
No preview · Article · Jan 2010 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: A 2 times 21.5-22.3 Gb/s to 4 times 10.7-11.2 Gb/s SF15.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 times 20 Gb/s data from a TIA and outputs SF15.2 4 times 10 Gb/s data and 10 Gb/s deskew channel. The serializer receives SF15.2 inputs and outputs 2 times 20 Gb/s for the optical DQPSK modulator. Although inductor-peaked CML is needed in the deserializer 20 Gb/s input limiting amplifier (LA) and the serializer output stages, power reduction to 3 W for both IC's is effected by deserializing to 16 times 2.5 Gb/s internally and implementing the core logic using standard CMOS circuits.
[Show abstract][Hide abstract] ABSTRACT: A CDR/deserializer IC is designed in 65nm triple-well CMOS, dissipates 1.3W, receives two 20.6–22.3Gb/s (DQPSK) data channels, and outputs 4⊲1 × 10.65−11.3Gb/s SFI5.2 data and deskew channel. The deserializer comprises two limiting amplifiers, a 2 × 20G to 16 × 2.5G CDR/DEMUX, a synchronizing FIFO, SFI5.2 deskew channel generator, and a 5×2.5 to 10G MUX. It also includes a 5GHz PLL, a a 2.5Gb/s PRBS and BERT, a temperature sensor, and an I2C bus.
[Show abstract][Hide abstract] ABSTRACT: This paper describes the prototype serializer (SER) IC for a 40 Gb/s optical transponder module featuring SFI5.2 input interface and two output modes, dual 20Gb/s and single 40Gb/s, to support SONET OC-768, SDH STM 256 and ITU G.709. The data rate covers from 21.5 to 22.3Gb/s for the dual-20Gb/s mode, and from 39.8 to 44.6Gb/s for the single-40Gb/s mode.