Young-Chan Jang

Kumoh National Institute of Technology, Sŏul, Seoul, South Korea

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Publications (29)7.43 Total impact


  • No preview · Article · Dec 2015 · Journal of Semiconductor Technology and Science
  • Kwang-Hun Lee · Young-Chan Jang
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    ABSTRACT: A scalable low voltage signaling (SLVS) transmitter, with asymmetric impedance calibration, is proposed for mobile applications which require low power consumption. The voltage swing of the proposed SLVS transmitter is scalable from 40mV to 440mV. The proposed asymmetric impedance calibration asymmetrically controls the pull-up and pulldown drivers for the SLVS transmitter with an impedance of 50 This makes it possible to remove the additional regulator used to calibrate the impedance of an output driver by controlling the swing level of a pre-driver. It also maintains the common mode voltage at the center voltage level of the transmitted signal. The proposed SVLS transmitter is implemented using a 0.18-μm 1-poly 6-metal CMOS process with a 1.2-V supply. The active area and power consumption of the transmitter are 250 × 123 μm2and 2.9mW/Gb/s, respectively. © 2014 The Institute of Electronics, Information and Communication Engineers.
    No preview · Article · Aug 2014 · IEICE Transactions on Electronics
  • Mungyu Kim · Hoon-Ju Chung · Young-Chan Jang
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    ABSTRACT: A 10-bit digital-to-analog converter (DAC) with a small area is proposed for data-driver integrated circuits of active-matrix liquid crystal display systems. The 10-bit DAC consists of a 7-bit resistor string, a 7-bit two-step decoder, a 2-bit logarithmic time interpolator, and a buffer amplifier. The proposed logarithmic time interpolation is achieved by controlling the charging time of a first-order low-pass filter composed of a resistor and a capacitor. The 7-bit two-step decoder that follows the 7- bit resistor string outputs an analog signal of the stepped wave with two voltage levels using the additional 1-bit digital code for the logarithmic time interpolation. The proposed 10-bit DAC is implemented using a 0.35- μm CMOS process and its supply voltage is scalable from 3.3V to 5.0V. The area of the proposed 10-bit logarithmic time interpolation DAC occupies 57% of that of the conventional 10-bit resistor-string DAC. The DNL and INL of the implemented 10-bit DAC are +0.29/-0.30 and +0.47/-0.36 LSB, respectively. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.
    No preview · Article · Jun 2014 · IEICE Transactions on Electronics
  • Pil-Ho Lee · Hyun Bae Lee · Young-Chan Jang
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    ABSTRACT: A 125 MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200 MHz is fabricated using a 0.18-mu m 1-poly 6-metal CMOS process with a 1.8 V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07 ps and 21.1 ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125 MHz. The area and power consumption of the implemented DLL are 0.3 mm(2) and 12.7 mW, respectively.
    No preview · Article · May 2014 · IEICE Transactions on Electronics
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    Pil-Ho Lee · Young-Chan Jang
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    ABSTRACT: This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are and 3.48 mW, respectively.
    Preview · Article · Feb 2014
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    Yeon-Ho Jeong · Young-Chan Jang
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    ABSTRACT: This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18- CMOS process and its active area is . The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.
    Preview · Article · Jan 2014
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    Kwang-Hun Lee · Young-Chan Jang
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    ABSTRACT: A 5.6-Gb/s/channel 4-pulse amplitude modulation (PAM) transceiver is designed for a high-bandwidth chip-to-chip interface in a display application. The asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margins, and the implemented scheme reduces the reference noise effect in a receiver by 33%. The proposed asymmetric 4-PAM transceiver is implemented by using a 0.13-μm 1-poly 6-metal CMOS process with a 1.2 V supply. The measured rms jitter of the output clock of the phase-locked loop (PLL) is 4.18 ps at the operating frequency of 700 MHz for 5.6-Gb/s/channel with a quad data rate scheme. The measurement results show that the proposed asymmetric 4-PAM signaling increases the voltage margin by 23.5% without reduction in the time margin as compared with conventional 4-PAM signaling when the noise magnitude of the single reference is 65 mV. The active area and power consumption of a 1-channel transceiver including the PLL are 0.294 μm2 and 6 mW/Gb/s, respectively.
    Preview · Article · Dec 2013 · International Journal of Control and Automation
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    Seung-Yong Lee · Pil-Ho Lee · Young-Chan Jang
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    ABSTRACT: Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.
    Preview · Article · Oct 2013
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    Han-Yeol Lee · Yu-Jeong Hwang · Young-Chan Jang
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    ABSTRACT: An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are and 6.71mW.
    Preview · Article · Oct 2013
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    Yeon-Ho Jeong · Young-Chan Jang
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    ABSTRACT: This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of is fabricated using a 0.18- CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.
    Preview · Article · Feb 2013
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    Mungyu Kim · Young-Chan Jang
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    ABSTRACT: In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to . The area and power consumption of the fabricated temperature sensor are and , respectively.
    Preview · Article · Feb 2013
  • Ji-Hun Eo · Yeon-Ho Jeong · Young-Chan Jang
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    ABSTRACT: An 8-bit 100-kS/s successive approximation (SA) analogto- digital converter (ADC) is proposed for measuring EEG and MEG signals in an 8 × 8 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SCDAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-μm 1-poly 6-metal CMOS process with a 3.3V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 μW and 0.059mm2, respectively. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.
    No preview · Article · Feb 2013 · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
  • Kwang-Hun Lee · Young-Chan Jang

    No preview · Article · Jan 2013
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    ABSTRACT: A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are and 193.02mW.
    Preview · Article · Sep 2012
  • Kwang-Hun Lee · Young-Chan Jang

    No preview · Article · Jun 2012
  • Ji-Hun Eo · Sang-Hun Kim · Young-Chan Jang

    No preview · Article · Jun 2012
  • Hyun Bae Lee · Young-Chan Jang
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    ABSTRACT: Mirrored serpentine microstrip lines are proposed for a parallel high speed digital signaling to reduce the peak far-end crosstalk (FEXT) voltage. Mirrored serpentine microstrip lines consist of two serpentine microstrip lines, each one equal to a conventional normal serpentine microstrip line. However, one serpentine microstrip line of the mirrored serpentine microstrip lines is flipped in the length direction, and thus, two serpentine microstrip lines face each other. Time domain reflectometry measurements show that the peak FEXT voltage of the mirrored serpentine microstrip lines is reduced by 56.4% of that of conventional microstrip lines and 30.0% of that of conventional normal serpentine microstrip lines.
    No preview · Article · Jun 2012 · IEICE Transactions on Electronics
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    Ji-Hun Eo · Sang-Hun Kim · Mun-Gyu Kim · Young-Chan Jang
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    ABSTRACT: A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18- 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.
    Preview · Article · Mar 2012
  • Han-Yeol Lee · Young-Chan Jang
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    ABSTRACT: A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2 GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.
    No preview · Article · Jan 2012 · IEICE Electronics Express
  • Ji-Hun Eo · Sang-Hun Kim · Young-Chan Jang
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    ABSTRACT: A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-mu m 1-poly 6-metal CMOS process with a I V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 mu W and 0.126 mm(2), respectively. The FoM is 47 fJ/conversion-step.
    No preview · Article · Nov 2011 · IEICE Transactions on Electronics