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ABSTRACT: A circuit block model and methodology for accurate power supply noise analysis, taking the impact of power supply noise on the current consumption into account, is presented. This enables high transient accuracy even at excessive power supply noise. Further improvement is obtained by an adaptive model for the capacitance of switching gates. Simulations for various power grids and test circuits are compared between a state of the art and the improved modelling. Simulation error of power supply noise was reduced by 4.7X - 20X at a simulation run time penalty of roughly 20%. This makes it especially helpful for low power SoC designs, with high transient IR-drop and multi-frequency domains, where transient accuracy is of concern.