[Show abstract][Hide abstract] ABSTRACT: We investigate threshold voltage shifts induced by heavy ions in sub 70-nm charge-trap cells, based on TaN-Al O -SiN-SiO -Si (TANOS) stack and compare the results with floating gate memories. Large shifts are observed, although to a smaller extent than in floating gate devices with similar feature size. Basic mechanisms leading to the heavy-ion induced charge loss/compensation in the storage layer are dis- cussed, considering hole injection from the blocking and the tunnel oxide. The applicability of the transient conductive path and the transient carrier flux models developed for floating gate memories is evaluated as well.
No preview · Article · Jun 2011 · IEEE Transactions on Nuclear Science
[Show abstract][Hide abstract] ABSTRACT: This paper presents a detailed investigation of the ISPP dynamics of charge-trap memory capacitors, considering not only the flat-band voltage but also the bottom oxide electric field and tunneling current evolution during programming. Differently from the floating-gate case, results on nitride-based memories show that the flat-band increase per step does not equal the step amplitude of the gate staircase, decreasing, moreover, as programming proceeds. As a consequence, the electric field and tunneling current through the bottom oxide are shown to largely increase. Using results at different temperatures and on samples with different stack compositions, this dynamics is explained in terms of a drop of the programming efficiency as more and more charge is stored in the nitride layer, due to the reduction of the number of free traps available for capturing the injected electrons.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a scaling analysis of the statistical distribution of the threshold voltage shift (Δ V <sub>T</sub>) obtained by electron storage in nitride memories, considering both its average and standard deviation. For fixed density of trapped charge, the average Δ V <sub>T</sub> decreases as a consequence of fringing fields, not predictable by any 1-D simulation approach. Moreover, the distribution statistical dispersion increases with technology scaling due to a more sensitive percolative substrate conduction in the presence of atomistic doping and 3-D electrostatics. The impact of these effects on device performance is then highlighted, showing that the accuracy of the staircase programming algorithm can be reduced further from the limitation given by the electron injection statistics during programming. The impact of electron storage in the nitride on random telegraph noise instabilities is also investigated, showing that, despite single cell behavior may be modified, negligible effects result at the statistical level.
No preview · Article · Oct 2010 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: We present a comprehensive investigation of the programming dynamics of nanoscale charge-trap memories, based on 3D Monte Carlo simulations accounting for: 1) true 3D electro-statics during programming and read; 2) atomistic substrate doping; 3) discrete traps, fluctuating in number and position, with localized electron storage; 4) discrete electron injection into traps. The model allows to clarify several key issues affecting the program operation of charge-trap memories, most notably the reduced slope of the ISPP transients exhibited by scaled cells, the programming variability, and the width of the final programmed threshold-voltage distribution. Results are of utmost importance for the assessment of the true programming performance of nanoscale charge-trap memory technologies.
No preview · Article · Jan 2010 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International