[Show abstract][Hide abstract] ABSTRACT: In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of pro-gram/erase speed, endurance and reliability.
[Show abstract][Hide abstract] ABSTRACT: We present the first-ever commercially available microcontroller families built with innovative split-gate based NOR flash memory that uses silicon nanocrystals as the storage medium. The 32-bit mixed-signal low-power Kinetis microcontroller families have nanocrystal based flash memories (referred to as TFS for ‘Thin Film Storage’) with a wide range of array sizes from 32KB to 1MB. In addition, the unique capability of TFS has enabled inclusion of fully configurable embedded EEPROM functionality called ‘FlexMemory’, which also manages wear leveling for high endurance. The TFS memory has been optimized to deliver read access time of
[Show abstract][Hide abstract] ABSTRACT: We show a 90nm nanocrystal-based split gate embedded flash memory that is able to meet the speed, endurance and reliability requirements for 32-bit microcontroller products. A 3.4V operating window is achievable and the process is robust and repeatable across many lots. Erase after 10k cycles can be achieved in 5ms, long-term data retention of cycled arrays is not susceptible to SILC-induced charge loss mechanisms, and program disturb can meet the needs of flash and EEPROM. (Keywords: Nanocrystals, Flash Memories, Embedded Flash, Source-side Injection, Endurance, Data Retention).
[Show abstract][Hide abstract] ABSTRACT: This paper presents a state-of-the-art 65nm SOI CMOS transistor technology target for high performance microprocessor application. N/PFET shows short channel control meeting manufacturing margin at 32/35nm respectively. By using dual contact etch stop layer (CESL) process, PFET ion is 875muA/mum at Ioff=100nA/mum (V DD=1.2V), which is 65% increase over 90nm node. The 65nm technology also offers SRAM cell sizes ranging from 0.499mum2 to 0.64mum2 for various speed and density requirement
No preview · Article · Apr 2006 · International Symposium on VLSI Technology, Systems, and Applications, Proceedings
[Show abstract][Hide abstract] ABSTRACT: In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated
[Show abstract][Hide abstract] ABSTRACT: We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures
[Show abstract][Hide abstract] ABSTRACT: The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages