[Show abstract][Hide abstract] ABSTRACT: In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.
[Show abstract][Hide abstract] ABSTRACT: In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm<sup>2</sup>, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm<sup>2</sup>) has a demonstrated Static Noise Margin (SNM) of 213 mV at 1 V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28 nm LP poly/SiON reference. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT~2mV.um) versus our previously-reported result. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k~2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.
[Show abstract][Hide abstract] ABSTRACT: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum<sup>2</sup> and 0.124 mum<sup>2</sup>. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T<sub>inv</sub> scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum<sup>2</sup> cell to meet low power application requirements.