Jose A. Villasante-Bembibre

Universitat Ramon Llull, Barcino, Catalonia, Spain

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Publications (2)0 Total impact

  • J. Albo-Canals · Jose A. Villasante-Bembibre · Jordi Riera-Babures · X. Vilasis-Cardona
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    ABSTRACT: This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split & Shift techniques to have a 12 �? 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I2C interfece to communicate with Lego Mindstorm Device.
    No preview · Article · Feb 2010
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an 8-bit FPGA implementation of a discrete time cellular neural network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 31 times 31 grid that processes more than 2500 images per second. As this work evolves from a previous binary DTCNN implementation, results are compared in terms of area occupancy, routing complexity and processing time. Several design techniques have been applied to optimize the VHDL implementation on an Altera Stratix II-EP2S60F484C5 FPGA device. Moreover, as technology independent description allows easy migration to other devices or vendors, the benefits of FPGA technology evolution are discussed, focusing on DTCNN implementations.
    No preview · Conference Paper · Sep 2009

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