[Show abstract][Hide abstract] ABSTRACT: Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness . Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells . When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.
[Show abstract][Hide abstract] ABSTRACT: A functional 4F<sup>2</sup> DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F<sup>2</sup> cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90Â°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F<sup>2</sup> DRAM.
No preview · Article · May 2010 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.
No preview · Article · Dec 2009 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: A transceiver chip with per-pin de-skew and read latency detection scheme utilizing on-chip TDR was implemented in 60nm DRAM process for the interface with source synchronous clock system. Without multi-phase clock, each time skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate. Also, the jitter reduction of 50% was measured with swing-level controlled voltage-mode driver in the absence of destination termination at 1.6-Gb/s.