Giovanni De Micheli

École Polytechnique Fédérale de Lausanne, Lausanne, Vaud, Switzerland

Are you Giovanni De Micheli?

Claim your profile

Publications (604)342.61 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: • Fabrication strategies of Au and Pt nanoparticle-based electrodes.
    No preview · Article · Feb 2016 · TrAC Trends in Analytical Chemistry

  • No preview · Article · Jan 2016 · IEEE Sensors Journal
  • Source
    Conference Paper: Spintronic Majority Gates
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper we present an overview of two types of majority gate devices based on spintronic phenomena. We compare the spin torque majority gate and the spin wave majority gate and describe work on these devices. We discuss operating conditions for the two device concepts, circuit implication and how these reflect on materials choices for device implementation.
    Full-text · Conference Paper · Dec 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a complete study is carried out investigating the relationship between the biosensing and the electrical characteristics of freestanding two-terminal Schottky-barrier silicon nanowires. This paper successfully reproduces computationally the electrical behavior obtained experimentally from the nanowire devices before and after the surface biomodification. Throughout modeling and simulations, this paper confirms that the experimental results obtained from the electrical characterization of bare two-terminal Schottky-barrier silicon nanowires present current-to-voltage characteristics fully equivalent to that of a pure memristor device, according to the literature. Furthermore, this paper shows that the voltage gap appearing in the current-to-voltage characteristics for nanowires with biomodified surface is related to capacitive effects due to minority carriers in the nanowire and it is also indicated that those effects are strongly affected by the concentration of antigens uptaken on the device surface. Overall, this paper confirms the implication of the memristive effect for biosensing applications and therefore, demonstrates the memristive biosensors.
    Preview · Article · Nov 2015 · IEEE Sensors Journal
  • [Show abstract] [Hide abstract]
    ABSTRACT: A system for wireless power transfer and data communication of implantable bio-monitoring systems is presented. The proposed solution uses a servo-controlled power transmitter moved under the animal moving space. An $x$ - $y$ movable magnetic coil transmits the required power with a level able to keep constant the received energy by the bio-sensor system. The power is transferred via the optimized remote powering link at 13.56 MHz. The received ac signal is converted to dc voltage with a passive full-wave integrated rectifier and the voltage regulator supplies 1.8 V for the implantable sensor system. The sensor control and readout circuit measures the current on the bio-sensors and transmit the data to the transmitter. The sensor data are transmitted to an external reader by a low-power OOK transmitter and received by a custom designed receiver at 869 MHz. The results are shown in a tablet computer in real time continuously. The long-term characterization of the implantable system is verified by a fully bio-compatible packaged implant with 30 days measurement. A complete prototype is also presented to prove the overall system performance with the experimental in vitro measurement.
    No preview · Article · Nov 2015 · IEEE Sensors Journal
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Novel methods to obtain Pt nanostructured electrodes have raised particular interest due to their high performance in electrochemistry. Several nanostructuration methods proposed in the literature use costly and bulky equipment or are time-consuming due to the numerous steps they involve. Here, Pt nanostructures were produced for the first time by one-step template-free electrodeposition on Pt bare electrodes. The change in size and shape of the nanostructures is proven to be dependent on the deposition parameters and on the ratio between sulphuric acid and chloride-complexes (i.e., hexachloroplatinate or tetrachloroplatinate). To further improve the electrochemical properties of electrodes, depositions of Pt nanostructures on previously synthesised Pt nanostructures are also performed. The electroactive surface areas exhibit a two order of magnitude improvement when Pt nanostructures with the smallest size are used. All the biosensors based on Pt nanostructures and immobilised glucose oxidase display higher sensitivity as compared to bare Pt electrodes. Pt nanostructures retained an excellent electrocatalytic activity towards the direct oxidation of glucose. Finally, the nanodeposits were proven to be an excellent solid contact for ion measurements, significantly improving the time-stability of the potential. The use of these new nanostructured coatings in electrochemical sensors opens new perspectives for multipanel monitoring of human metabolism.
    Full-text · Article · Oct 2015 · Scientific Reports
  • Pierre-Emmanuel Gaillardon · Xifan Tang · Gain Kim · Giovanni De Micheli
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we investigate the opportunity brought by controllable-polarity transistors to design efficient reconfigurable circuits. Controllable-polarity transistors are devices whose polarity can be electrostatically programmed to be either n- or p-type. Such devices are used to build ultrafine grain computation cells. These cells are arranged into regular matrices, called MClusters, with a fixed and incomplete interconnection pattern, employed to minimize the reconfigurable interconnection overhead. We subsequently use them into field-programmable gate arrays (FPGAs). To assess this architectural scheme in an efficient and objective manner, we present a complete benchmarking tool flow and focus on the packing algorithm developed to handle the architecture. We finally perform the evaluation with widely used benchmark circuits. Leveraging the ultrafine grain cells compactness from a system-level perspective, we show that FPGAs exploiting MClusters demonstrate average savings of 43% and 23% in area and delay, respectively, as compared with the CMOS lookup table FPGA counterpart at 22-nm technological node.
    No preview · Article · Oct 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Shashikanth Bobba · Giovanni De Micheli
    [Show abstract] [Hide abstract]
    ABSTRACT: As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits, thereby opening up venues for new transistor channel materials based on nanowires and nanotubes. Transistors based on nanowires and nanotubes inherently exhibit ambipolar behavior. While technologists aim to suppress ambipolar behavior of these transistors, new design methodologies are proposed by exploiting the phenomenon of controllable polarity. In this paper, we propose regular layout fabrics, with an emphasis on silicon nanowires (SiNWs) as the candidate technology. A double-gate ambipolar SiNW field-effect transistor operates as p-type or n-type by electrically controlling the polarity of the second gate. We propose layout techniques to address gate-level routing congestion, as every transistor has two gates to route. Novel symbolic layouts, which are technology independent, are proposed for ambipolar circuits. In the second part of this paper, we present an approach for designing an efficient regular layout called sea-of-tiles (SoTs). A logic tile is essentially an array of prefabricated transistor-pairs grouped together. We design four logic tiles, which form the basic building block of the SoT fabric. We run extensive comparisons of mapping standard benchmarks onto the SoT fabric to find the optimum tile. This paper shows that SoT with and , on an average, outperforms the one with by 16% and 14% in area utilization, respectively.
    No preview · Article · Oct 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Source
    Somayyeh Rahimian Omam · Xifan Tang · P.-E. Gaillardon · Giovanni De Micheli
    [Show abstract] [Hide abstract]
    ABSTRACT: Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switches, routing structures are mainly responsible for the performance limitation. Hence, employing more efficient switches can drastically improve the performance and reduce the power consumption of the FPGA. Resistive Random Access Memory (RRAM)-based switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. The lower RC delay of RRAM-based routing multiplexers, as compared to CMOS-based routing structures encourages us to reconsider the buffer distribution in FPGAs. This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs. Our architectural simulations show that the use of RRAM switches improves the critical path delay by 56% as compared to CMOS switches in standard FPGA circuits at 45-nm technology node while, at the same time, the area and power are reduced, respectively, by 17% and 9%. By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based FPGAs.
    Preview · Article · Sep 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced technology scaling and power density increase, inexact circuits appear to be very promising as a solution. In this paper, we present a novel pruning technique developed as a logic level method to select and prune parts of a digital circuit. The error is computed at each pruning step using probabilistic error propagation and Hamming distance computation, making the evaluation possible at runtime. The technique was validated on several parallel adder architectures. Experimental results proved the efficiency of the technique with Energy-Delay-Area product reduction of 1.8× for less than 10-4% of relative error on the considered benchmarks at 45-nm technology node.
    Preview · Article · Sep 2015
  • Source
    N. Aliakbarinodehi · Giovanni De Micheli · Sandro Carrara
    [Show abstract] [Hide abstract]
    ABSTRACT: Nanostructured biosensors with the aim of electroactive cancer-drug detection were investigated. The aim of this work is improvement of the sensitivity and limit of detection of two differently nanostructured biosensors to find out the best choice for quantifying the concentration of etoposide, as a widely used electroactive cancer drug, in its therapeutic range. To this purpose etoposide concentrations, ranging from zero to 60 μM, were sensed at multi-walled carbon nanotube and gold nanoparticle functionalized bioelectrodes using cyclic voltammetry. The optimum scan rate for voltammetric experiments was found out equal to 70 mV s-1 and 130 mV s-1 for multi-walled carbon nanotube and gold nanoparticle based electrodes, respectively. For nanostructuring the electrodes, the optimum nanomaterial mass were experimentally obtained for multi-walled carbon nanotube and gold nanoparticle based electrodes equal to 20 μ g (4314 mm of additional electroactive surface area) and 104 g (6471 mm of additional electroactive surface area), respectively. Bioelectrodes produced based on this optimized configurations showed sensitivity of 0.98 ± 0.41 μA μM-1 cm-2 and 1.43 ± 0.26 μA μM-1 cm-2, and limit of detection of 1.52 ± 0.89 μM and 1.29 ± 0.48 μM for multi-walled carbon nanotube and gold nanoparticles based electrodes. Comparing the limit of detection achieved in this work with the therapeutic range of etoposide verifies the possibility of using both nanostructured bioelectrodes for etoposide detection. However, gold nanoparticle based electrodes exhibit better electrochemical improvements in terms of both sensitivity and limit of detection.
    Preview · Article · Sep 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall- around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.
    Preview · Article · Sep 2015 · ACM Journal on Emerging Technologies in Computing Systems
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180 nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized. A low-cost integration method is applied to the developed TaOx-based memories to achieve chip level ReRAM–CMOS integration. The integrated memory devices show working voltages compatible with CMOS circuits operations. Measured SET and RESET voltages of the ReRAM integrated cells are −1 V and +1.3 V, respectively, demonstrating suitability for low-voltage applications.
    Full-text · Article · Sep 2015 · Microelectronic Engineering
  • Ioulia Tzouvadaki · C. Parrozzani · A. Gallotta · Giovanni De Micheli · Sandro Carrara
    [Show abstract] [Hide abstract]
    ABSTRACT: Prostate cancer is the most common cancer among men except for skin cancer, and the detection at early stages is crucial. In the present work, nanofabricated memristive biosensors are subjected to surface bio-modification targeting at prostate-specific antigen (PSA) IgM detection. The electrical response of the nanofabricated devices examined before and after the bio-modification achieves a label-free detection for three biomarker concentrations. The presence of biomolecules linked to the surface of the nanostructures is detected by a voltage gap appearing in the memristive electrical characteristics. Enzyme-linked immunosorbent assay methodology is further applied to verify the efficiency of the application of diverse biomarker concentrations on the surface. Scanning electron microscopy shows details on the morphology of the nanofabricated structures before and after the bio-modification, and confocal microscopy is implemented to obtain a 3D fluorescent signal distribution of the biomolecules. The system shows the potential for applications in molecular diagnostics and for implementation targeting at the early detection of the prostate cancer disease.
    No preview · Article · Aug 2015 · BioNanoScience
  • [Show abstract] [Hide abstract]
    ABSTRACT: Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high-performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance.
    No preview · Article · Aug 2015 · Proceedings of the IEEE
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The development of fast and mobile drug detection is an important aspect of personalized medicine. It enables the quick assessment of inter-individual differences in drug metabolism and corresponding adjustments of the dose. Recent developments of amperometric biosensors using cytochrome P450 (CYP) show great promise, by lowering the detection limit to physiological range for several drugs via the usage of Multi Walled Carbon Nanotubes (MWCNT). The next challenge is to develop algorithms for processing the resulting sensor data compatible with low-power hardware, which would allow the development of portable battery-powered devices. In this work we pursue a novel approach to this problem. Here we provide a proof of principle by demonstrating how sensor data could be analyzed using a conventional multi-layer perceptron network with error-backpropagation.
    Preview · Conference Paper · Jul 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Ultrasound imaging is a technique widely used in medicine to visualize organs and other body structures, capturing their position, size, morphology and any pathological lesions. Its use is unfortunately limited to specialized centers with trained personnel, and it would be bene�cial to expand its applicability to environments like on-the-�eld emergency response and family physician cabinets. This requires the development of new ultrasound platforms that must be faster, lower-power, easier to use, safe and reliable. One of the major challenges to be met is to dynamically manage a myriad of di�erent imaging options and con�guration parameters, which impact image quality and computation cost at the same time. Focusing on this challenge, in this paper we fi�rst give an overview of ultrasound imaging techniques and of their possible con�guration and parameterization options. We then discuss the impact of these options on computation cost and image quality, showing outcomes from a prototype Matlab ultrasound imaging pipeline.
    Full-text · Conference Paper · Apr 2015
  • Source
    Luca Amarù · Gage Hills · P.-E. Gaillardon · Subhasish Mitra · Giovanni De Micheli
    [Show abstract] [Hide abstract]
    ABSTRACT: Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Researchers face then the question: How many gates do we need? In this paper, we address the logic side of this question. We determine whether or not an increasing number of gates leads to more compact logic implementations. For this purpose, we develop a logic synthesis flow that intrinsically exploits a MIGFET switching function. Using simplified design assumptions and device/interconnect models, we synthesize MCNC benchmarks on 5 promising MIGFET devices, with number of gates ranging from 1 to 7. Experimental results evidence nontrivial area/delay/energy minima, located between 1 and 4 gates, depending on a MIGFET switching function and device/interconnect technology.
    Preview · Article · Mar 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Manipulating logic functions via majority operators recently drew the attention of researchers in computer science. For example, circuit optimization based on majority operators enables superior results as compared to traditional logic systems. Also, the Boolean satisfiability problem finds new solving approaches when described in terms of majority decisions. To support computer logic applications based on majority a sound and complete set of axioms is required. Most of the recent advances in majority logic deal only with ternary majority (MAJ- 3) operators because the axiomatization with solely MAJ-3 and complementation operators is well understood. However, it is of interest extending such axiomatization to n-ary majority operators (MAJ-n) from both the theoretical and practical perspective. In this work, we address this issue by introducing a sound and complete axiomatization of MAJ-n logic. Our axiomatization naturally includes existing majority logic systems. Based on this general set of axioms, computer applications can now fully exploit the expressive power of majority logic.
    Full-text · Article · Feb 2015 · IEEE Transactions on Computers
  • Source
    Sungroh Yoon · Nahmsuk Oh · Peivand Tehrani · Eui-Young Chung · Giovanni De Micheli
    [Show abstract] [Hide abstract]
    ABSTRACT: We propose a method called Fast and Realistic Attacker Modeling and Evaluation (FRAME) that can reduce pessimism in static noise analysis by exploiting temporal logical correlation of attackers and using novel techniques termed envelopes and $\sigma$ functions. Unlike conventional pruning-based approaches, FRAME efficiently considers all relevant attackers, thereby producing more realistic results. FRAME was tested with complex industrial design and successfully reduced the pessimism of conventional techniques by 30.4% on average, with little computational overhead.
    Preview · Article · Feb 2015

Publication Stats

17k Citations
342.61 Total Impact Points


  • 2005-2015
    • École Polytechnique Fédérale de Lausanne
      • • Integrated Systems Laboratory
      • • Microelectronic Systems Laboratory
      Lausanne, Vaud, Switzerland
    • STMicroelectronics
      Genève, Geneva, France
    • CSL Behring
      King of Prussia, Pennsylvania, United States
  • 2014
    • École Polytechnique
      Paliseau, Île-de-France, France
  • 2009-2014
    • Eawag: Das Wasserforschungs-Institut des ETH-Bereichs
      Duebendorf, Zurich, Switzerland
    • EPF Ecole d'ingénieurs
      Sceaux-l'Unité, Île-de-France, France
  • 2013
    • The University of Manchester
      Manchester, England, United Kingdom
    • Integrated Laboratory Systems
      North Carolina, United States
  • 2010-2011
    • Ecole polytechnique fédérale de Lausanne
      Lausanne, Vaud, Switzerland
  • 1999-2011
    • University of Bologna
      • "Guglielmo Marconi" Department of Electrical, Electronic and Information Engineering DEI
      Bolonia, Emilia-Romagna, Italy
  • 2008
    • Swiss Institute of Bioinformatics
      • Vital-IT Group
      Lausanne, Vaud, Switzerland
  • 2007
    • Università degli Studi di Urbino "Carlo Bo"
      Urbino, The Marches, Italy
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 1988-2007
    • Stanford University
      • • Computer Systems Laboratory
      • • Department of Electrical Engineering
      • • Center for Integrated Systems
      Palo Alto, California, United States
  • 2006
    • Università degli studi di Cagliari
      • Department of Electrical and Electronic Engineering
      Cagliari, Sardinia, Italy
  • 2001
    • Synopsys
      Mountain View, California, United States
  • 1998
    • Georgia Institute of Technology
      • School of Electrical & Computer Engineering
      Atlanta, GA, United States
  • 1994
    • University of Illinois, Urbana-Champaign
      Urbana, Illinois, United States
  • 1985
    • IBM
      • Thomas J. Watson Research Center
      Armonk, New York, United States
  • 1982-1984
    • University of California, Berkeley
      • Department of Electrical Engineering and Computer Sciences
      Berkeley, California, United States