G. Roy

University of Glasgow, Glasgow, Scotland, United Kingdom

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Publications (66)56.71 Total impact

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    ABSTRACT: Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-$\kappa/\hbox{metal}$ gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage.
    No preview · Article · May 2012 · IEEE Electron Device Letters
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    ABSTRACT: For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.
    No preview · Article · Jan 2012 · IEEE Transactions on Electron Devices
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    ABSTRACT: A comprehensive statistical investigation of the increase in resistance associated with charge trapping in 'atomistic' simulations is presented considering a wide range of doping densities and mesh spacing for both classical and quantum formalisms. A modified mobility model for the 'atomistic' simulations is proposed to suppress the error related to the fictitious charge trapping.
    Preview · Article · Sep 2011
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    ABSTRACT: It has been shown that sub 100nm SRAM is particularly sensitive to stochastic device variability. In this paper we consider two correlated figures of merit for SRAM, Static Noise Margin (SNM) and Read Current. For the purposes of this paper 1,000 3D atomistic simulations of microscopically different 25nm P and N bulk MOSFETs were performed, and statistical compact models were then extracted for each device. Using these models simulations are performed to calculate the SNM and Read Current distributions of SRAM cells constructed using devices from the device ensemble. Variability in device performance has been then introduced via Gaussian or skewed Gaussian threshold voltages (Vt) and by using values of Vt extracted directly from the individual device compact models and the results of these simulations are then compared to the baseline simulations using fully extracted models. The results clearly demonstrate the errors that can be introduced in the estimation of SNM and Read Current distribution of a 6T SRAM cell when statistical device variability is not correctly modelled.
    Full-text · Article · Sep 2011
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    ABSTRACT: This paper presents a comprehensive full-scale three-dimensional simulation scaling study of the statistical threshold-voltage variability in bulk high- k /metal gate (HKMG) MOSFETs with gate lengths of 35, 25, 18, and 13 nm. Metal gate granularity (MGG) and corresponding workfunction-induced threshold-voltage variability have become important sources of statistical variability in bulk HKMG MOSFETs. It is found that the number of metal grains covering the gate plays an important role in determining the shape of the threshold-voltage distribution and the magnitude of the threshold-voltage variability in scaled devices in the presence of dominant variability sources (MGG, random discrete dopants, and line edge roughness). The placement of metal grains is found to also contribute to the total MGG variability. This paper presents the relative importance of MGG compared with other statistical variability sources. It is found that MGG can distort and even dominate the threshold-voltage statistical distribution when the metal grain size cannot be adequately controlled.
    No preview · Article · Aug 2011 · IEEE Transactions on Electron Devices
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    ABSTRACT: The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed.
    Full-text · Article · Dec 2010
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    ABSTRACT: With the scaling of field-effect transistors to the nanometre scale, it is well recognised that TCAD simulations of such devices need to account for quantum mechanical confinement effects. The most widely used method to incorporate quantum effects within classical and semi-classical simulators is via density gradient quantum corrections. Here we present our methodologies for including the density gradient method within our Drift-Diffusion and Monte Carlo simulators and highlight some of the additional benefits that this provides when dealing with the charge associated with random discrete dopants. KeywordsDensity gradient-Quantum corrections-Drift-Diffusion-Monte Carlo-Simulation-MOSFETs
    No preview · Article · Dec 2010 · Journal of Computational Electronics
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    ABSTRACT: An efficient method to accurately capture quantum confinement effects within Monte Carlo (MC) simulation while simultaneously resolving `ab initio' ionized impurity scattering via the density gradient (DG) formalism is presented. The model is applied to study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. Such simulations result in an increase in drain current variability when compared with similarly quantum corrected drift diffusion (DD) simulation. Following this, an efficient three-stage hierarchical strategy is presented that propagates the increased on-current variability captured in 3D quantum corrected `ab initio' MC into efficient 3D DD simulations that are in turn used to obtain target ID-VG characteristics for the extraction of statistical compact models.
    No preview · Conference Paper · Nov 2010
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    ABSTRACT: Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano-CMOS transistors. Such simulations result in an increased drain current variability when compared with the drift diffusion (DD) simulation. For the first time, a method that is used to accurately transfer the increased on-current variability obtained from the “ ab initio” MC simulations to the DD simulations is subsequently presented. The MC-corrected DD simulations are used to produce the target I-V characteristics from which the statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development.
    No preview · Article · Nov 2010 · IEEE Transactions on Electron Devices
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    ABSTRACT: Statistical variability associated with discreteness of charge and granularity of matter is one of limiting factors for CMOS scaling and integration. The major MOSFET statistical variability sources and corresponding physical simulations are discussed in detail. Direct statistical parameter extraction approach is presented and the scalability of 6T and 8T SRAM of bulk CMOS technology is investigated. The standard statistical parameter generation approaches are benchmarked and newly developed parameter generation approach based on nonlinear power method is outlined.
    No preview · Conference Paper · Oct 2010
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    ABSTRACT: Statistical variability (SV) is one of the fundamental limiting factors for future nano- CMOS scaling and integration of. Variability aware design is essential to achieve reasonable yield and reliability in the manufacture of circuit and systems. To develop effective variability aware design technologies it is essential to have a reliable and accurate statistical compact modeling strategy. In this study a nonlinear power method (NPM) based statistical compact modeling strategy is presented. The results indicate that statistical compact model parameters generated by a NPM approach are significantly better at capturing the tails and non-normal shape of statistical parameter distributions when compared with principal component analysis (PCA).
    Full-text · Conference Paper · Oct 2010
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    ABSTRACT: The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS) technology to achieve faster devices and higher device density and to reduce the cost per function has fueled the phenomenal growth and success of the semiconductor industry—captured over the past 40 years by Moore’s famous law. The International Technology Roadmap for Semiconductors (ITRS) predicts, as illustrated in Table 7.1, that 7-nm physical-gate-length CMOS transistors will be in mass production in 2018. The Roadmap of the leading integrated circuit (IC) manufacturer, IBM, goes further (see Table 7.2), predicting that the physical length of the transistors will reach 3 nm by 2025. Indeed, transistors with a 45-nm channel length are in mass production now in the 90-nm technology node and functioning transistors with a 4-nm channel length have been demonstrated already by NEC at IEDM 2003. Although it is clear that the scaling of the CMOS transistors will continue in the next two decades, it is widely recognized that intrinsic parameter fluctuations introduced by the discreteness of charge and matter will be a major factor limiting the integration of such devices with molecular dimensions in giga-transistor count chips. TABLE 7.1. Extract from theInternational Technology Roadmap forSemiconductors 2003. TABLE 7.2. IBMRoadmap, Dec. 2003.
    No preview · Chapter · May 2010
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    ABSTRACT: The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.
    No preview · Article · May 2010 · IEEE Design and Test of Computers

  • No preview · Article · Mar 2010 · IEEE Design and Test of Computers
  • B. Bindu · B. Cheng · G. Roy · X. Wang · S. Roy · A. Asenov
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    ABSTRACT: This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I–V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.
    No preview · Article · Mar 2010 · Solid-State Electronics
  • D. Reid · C. Millar · G. Roy · S. Roy · A. Asenov
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    ABSTRACT: Using 3D simulations of statistical ensembles of unprecedented size, we have studied statistical threshold voltage variations induced by the combined effects of random dopants and line edge roughness in a state of the art 35 nm MOSFET. Statistical samples of 10<sup>5</sup> microscopically different transistors have been simulated. Based on careful statistical analysis of the simulation results we have developed statistical enhancement techniques, which deliver a high degree of statistical accuracy at a greatly reduced computational cost.
    No preview · Conference Paper · Jan 2010
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    ABSTRACT: The UK e-Science EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS – www.nanocmos.ac.uk) was funded to address the challenges facing the global electronics semiconductor industry caused by the decreasing size of Complementary Metal Oxide Semiconductor (CMOS) transistors and the atomic variability present in devices manifest at these dimensions. Fundamental problems to be addressed include the modelling, understanding and predicting the effect of differences in the atomic structure of devices on their behaviour, and then using this information to guide electronic circuit and system designers who utilise CMOS components. In this paper we describe the e-Infrastructure that has been developed as part of the nanoCMOS project and outline how it supports large scale high performance computing (HPC) simulations of ensembles of devices which can subsequently be used to model and understand the impact that they have on very large electronic circuits. Key features of this e-Infrastructure include the support for very large scale HPC utilization; dealing with federated data sets and associated metadata from multi-level simulations, and addressing challenges related to security and intellectual property protection of both input and output data, simulation codes and electronic designs as a whole.
    No preview · Article · Jan 2010

  • No preview · Article · Jan 2010 · IEEE Design and Test of Computers
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    ABSTRACT: Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical circuit simulations.
    Full-text · Conference Paper · Jan 2010
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    ABSTRACT: Using the Glasgow ldquoatomisticrdquo simulator, we have performed 3D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of 10<sup>5</sup> or more microscopically different transistors. Simulation on such an unprecedented scale has been enabled by grid technology, which allows the distribution and the monitoring of very large ensembles on heterogeneous computational grids, as well as the automated handling of large amounts of output data. The results of these simulations show a pronounced asymmetry in the distribution of the MOSFET threshold voltages, which increases with transistor scaling. A comprehensive statistical analysis enabled by the large sample size reveals the origin of this observed asymmetry, provides a detailed insight into the underlying physical processes, and enables the statistical enhancement of simulations of random-dopant-induced threshold voltage variation.
    No preview · Article · Nov 2009 · IEEE Transactions on Electron Devices

Publication Stats

973 Citations
56.71 Total Impact Points


  • 2003-2011
    • University of Glasgow
      • • School of Engineering
      • • Division of Electronics and Electrical Engineering
      Glasgow, Scotland, United Kingdom
  • 2002
    • Universidad de Valladolid
      Valladolid, Castille and León, Spain