[Show abstract][Hide abstract] ABSTRACT: A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.
No preview · Article · Feb 2009 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm<sup>2</sup> compared to 0.079 Gb/mm<sup>2</sup> on D2 chips, as previously reported (K. Takeuchi et al.,2006). This is a 41% improvement in Gb/mm<sup>2</sup> and a 20% gain in overall die-size.