P. Maj

AGH University of Science and Technology in Kraków, Cracovia, Lesser Poland Voivodeship, Poland

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Publications (63)40.87 Total impact

  • K. Kasinski · P. Maj · P. Grybos · A. Koziol
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    ABSTRACT: We present three hardware solutions designed for a detector module built with a 2 cm × 2 cm hybrid pixel detector built from a single 320 or 450 μ m thick silicon sensor designed and fabricated by Hamamatsu and two UFXC32k readout integrated circuits (128 × 256 pixels with 75μ m pitch, designed in CMOS 130 nm at AGH-UST). The chips work in a single photon counting mode and provide ultra-fast X-ray imaging. The presented hardware modules are designed according to requirements of various tests and applications: ⋅Device A: a fast and flexible system for tests with various radiation sources. ⋅Device B: a standalone, all-in-one imaging device providing three standard interfaces (USB 2.0, Ethernet, Camera Link) and up to 640 MB/s bandwidth. ⋅Device C: a prototype large-area imaging system. The paper shows the readout system structure for each case with highlighted circuit board designs with details on power distribution and cooling on both FR4 and LTCC (low temperature co-fired ceramic) based circuits.
    No preview · Article · Feb 2016 · Journal of Instrumentation
  • P. Kmon · P. Maj · P. Gryboś · R. Szczygieł
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    ABSTRACT: We present a new method of an in-pixel threshold dispersion correction implemented in a prototype readout integrated circuit (IC) operating in a single photon counting mode. The new threshold correction method was implemented in a readout IC of area 9.6× 14.9 mm2 containing 23552 square pixels with the pitch of 75 μm designed and fabricated in CMOS 130 nm technology. Each pixel of the IC consists of a charge sensitive amplifier, a shaper, two discriminators, two 14-bit counters and a low-area trim DACs for threshold correction. The user can either control the range of the trim DAC globally for all the pixels in the integrated circuit or modify the trim DACs characteristics locally in each pixel independently. Using a simulation tool based on the Monte-Carlo methods, we estimated how much we could improve the offset trimming by increasing the number of bits in the trim DACs or implementing additional bits in a pixel to modify the characteristics of the trim DACs. The measurements of our IC prototype show that it is possible to reduce the effective threshold dispersion in large-area single-photon counting chips below 10 electrons rms.
    No preview · Article · Jan 2016 · Journal of Instrumentation
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    ABSTRACT: Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASIC's capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.
    No preview · Article · Dec 2015 · Journal of Instrumentation
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    Full-text · Dataset · Dec 2015
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    ABSTRACT: Designing a hybrid pixel detector readout electronics operating in a single photon counting mode is a very challenging process, where many main parameters are optimized in parallel (e.g. gain, noise, and threshold dispersion). Additional requirements for a smaller pixel size with extended functionality push designers to use new deep sub-micron technologies. Minimizing the channel size is possible, however, with a decreased pixel size, the charge sharing effect becomes a more important issue. To overcome this problem, we designed an integrated circuit prototype produced in CMOS 40 nm technology, which has an extended functionality of a single pixel. A C8P1 algorithm for the charge sharing effect compensation was implemented. In the algorithm's first stage the charge is rebuilt in a signal rebuilt hub fed by the CSA (charge sensitive amplifier) outputs from four neighbouring pixels. Then, the pixel with the biggest amount of charge is chosen, after a comparison with all the adjacent ones. In order to process the data in such a complicated way, a certain architecture of a single channel was proposed, which allows for: ⋅ processing the signal with the possibility of total charge reconstruction (by connecting with the adjacent pixels), ⋅ a comparison of certain pixel amplitude to its 8 neighbours, ⋅ the extended testability of each block inside the channel to measure CSA gain dispersion, shaper gain dispersion, threshold dispersion (including the simultaneous generation of different pulse amplitudes from different pixels), ⋅ trimming all the necessary blocks for proper operation. We present a solution for multistage gain and offset trimming implemented in the IC prototype. It allows for minimization of the total charge extraction errors, minimization of threshold dispersion in the pixel matrix and minimization of errors of comparison of certain pixel pulse amplitudes with all its neighbours. The detailed architecture of a single channel is presented together with experimental results and an algorithm for proper gain and offset trimming for better uniformity of the pixel matrix.
    No preview · Article · Dec 2015 · Journal of Instrumentation
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    ABSTRACT: The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn-Pb balls placed on a 320-μm pitch, yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. A successful completion of the 3-D integration is reported. In addition, all pixels in the matrix of 64 x 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e⁻ rms and a conversion gain of 69.5 μV/e⁻ with 2.6 e⁻ rms and 2.7 μV/e⁻ rms pixel-to-pixel variations, respectively, were measured.
    No preview · Article · Jul 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: Single Photon Counting architectures used in X-ray pixel imaging systems have superior performance (essentially infinite dynamic range, noiseless imaging, possibility of photons' counting only within a given energy window), however they offer only a limited photon count rate performance per single pixel. This paper presents a novel architecture of front-end readout electronics, which due to digitally assisted charge sensitive amplifier improves significantly count rate performance of these systems and allows to keep the low noise of the front-end electronics at the same time. The proposed architecture was amalyzed in 40 nm CMOS process. The simulations show that the single photon counting architecture operates correctly with frequency of input pulses fin = 4 MHz and has Equivalent Noise Charge ENC = 70 el. rms only (for detector capacitance CDET = 150 fF).
    No preview · Article · Jun 2015
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    ABSTRACT: The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80 μm) were also bonded to silicon pixelated sensors (with a pixel pitch of 100 μm) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39 e- and 70 e- , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52 μV/e- as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational.
    No preview · Article · Feb 2015 · IEEE Transactions on Nuclear Science
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    ABSTRACT: The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of 18 ×24 pixels with the pixel size of 100 μm ×100 μm. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is 84e- rms (for the peaking time of 48 ns), the gain is 79.7 μV/e-, while the effective threshold dispersion is 21e- rms.
    No preview · Article · Feb 2015 · IEEE Transactions on Nuclear Science
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    ABSTRACT: Advances in semiconductor technologies, enable the design of hybrid pixel detectors with ever smaller pixel sizes while maintaining good performance of analogue circuits. Along with the decrease in the size of pixels new, previously unaddressed phenomena are beginning to play an important role. One such phenomenon is the charge sharing effect, where the charge generated by a particle in the vicinity of the pixel's border is collected by two or more different detector electrodes and processed in part by two or more independent pixels. In systems operating in the single photon counting (SPC) mode which compares the amplitude of the recorded signal with a predetermined threshold, this may reduce or increase the number of photons counted. In systems which measure the amplitude of the signal recorded, this phenomenon can lead to incorrect results of the amplitude measurements. In order to investigate the effect of charge sharing, measurements were conducted using silicon pixel detectors with the thickness of 300 μ m and 1 mm, 100 μ m × 100 μ m pixel size, connected to the PXD18k ASIC. The pixel array was scanned with 16 keV narrow pencil beam. The measurement setup and the results of the measurements are presented in the article.
    No preview · Article · Feb 2015 · Journal of Instrumentation
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    ABSTRACT: The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.
    No preview · Article · Dec 2014 · Journal of Instrumentation
  • P. Maj · P. Grybos · P. Kmon · R. Szczygiel
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    ABSTRACT: We report on the novel method of an in-pixel offset and gain correction for implementation in multichannel hybrid detector readout circuits. A prototype ASIC consisting of 23552 square shaped pixels of 75 μm pitch was designed and fabricated in CMOS 130 nm technology. Each pixel containing charge sensitive amplifier, shaper, discriminator, correction circuits and two 14-bit counters has an equivalent noise charge of 89 e- rms and dissipates only 25 μW. Tests prove its exceptional uniformity with an offset spread of 19e- rms and the gain spread of only 3%, rms what is good enough for color X-Ray imaging. The paper presents the architecture of the ASIC, a transistor level novel schematic of key blocks used for offset and gain trimming, the testing procedure and its results.
    No preview · Conference Paper · Sep 2014
  • P Maj
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    ABSTRACT: An important trend in the design of readout electronics working in the single photon counting mode for hybrid pixel detectors is to minimize the single pixel area without sacrificing its functionality. This is the reason why many digital and analog blocks are made with the smallest, or next to smallest, transistors possible. This causes a problem with matching among the whole pixel matrix which is acceptable by designers and, of course, it should be corrected with the use of dedicated circuitry, which, by the same rule of minimizing devices, suffers from the mismatch. Therefore, the output of such a correction circuit, controlled by an ultra-small area DAC, is not only a non-linear function, but it is also often non-monotonic. As long as it can be used for proper correction of the DC operation points inside each pixel, it is acceptable, but the time required for correction plays an important role for both chip verification and the design of a big, multi-chip system. Therefore, we present two algorithms: a precise one and a fast one. The first algorithm is based on the noise hits profiles obtained during so called threshold scan procedures. The fast correction procedure is based on the trim DACs scan and it takes less than a minute in a SPC detector systems consisting of several thousands of pixels.
    No preview · Article · Jul 2014 · Journal of Instrumentation
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    ABSTRACT: For many years hybrid pixel detectors working in the single photon counting mode have been used not only in high energy physics experiments but also for X-ray imaging applications. In these detectors each pixel has its independent electronic readout channel for photon by photon signal processing, what provides better image quality and possibility of counting photons only within a given energy window. There are different trends in development of hybrid pixel detectors. One is to use nanometer or 3D technologies to include more complex functionality in single pixel cell together with good parameters of analog front-end electronics and high maximum pulse throughput per single channel. Another trend is targeted at building large area X-ray cameras which can be used by industry or novel scientific experiments mainly in material science, physics and biology. In both trends the problems to be solved are similar, however the priorities are a little bit different. This paper presents the main issues related to the development of semiconductor pixel detector systems on the examples of produced integrated circuits.
    No preview · Conference Paper · Jun 2014
  • Piotr Maj
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    ABSTRACT: Hybrid pixel detectors working in single photon counting mode are very attractive solution for new experiments as their functionality increases and the single pixel size is getting smaller. This is possible due to new deep sub-micron technologies, which allows making smaller devices. However, making smaller devices has drawbacks, one of which is that matching of smaller transistors decreases, resulting in higher offset spread of DC operating points in channels. Having large area pixel detector containing over 20.000 channels an efficient correction circuit is required in each channel allowing effective trimming of the entire matrix including small percentage of exceptional pixels. If the readout circuit contains a discriminator, different correction circuits are used for minimization of the mismatch effect usually at the discriminator input. As the pixel size is minimized correction DACs quality is often degraded and therefore it is not only non-linear but also likely non-monotonic. The large multi-thousand channel systems requires fast calculation of the correction DACs values in order to make the whole system useful. The correction scheme implemented in the large area hybrid pixel detector readout circuit containing 23552 pixels with a size of 100um x 100um each will be presented together with adequate measurements and applied correction algorithms.
    No preview · Conference Paper · Apr 2014
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    ABSTRACT: A hybrid pixel detector operating in a single photon counting mode requires a pixel readout chip with the geometry that matches the geometry of the detector array. Stringent and growing requirements on smaller pixel size, higher data throughput and more sophisticated functionality are imposed for such imaging systems. CMOS nanometer or 3D technologies seem to be very attractive for pixel readout integrated circuits, especially in the case of implementing more complex functionality or advanced algorithms on the chip. However, these technologies are mainly driven by high density and very fast digital circuits, nevertheless in case of hybrid pixel detectors the analog performance of front-end electronics, such as noise, offset spreads or crosstalk minimization, are of primary importance. We will present some examples of our realization of these kind of ICs both in advance technologies (like 3D or 40 nm CMOS), as well as for commercial application where final yield is of primary importance.
    No preview · Conference Paper · Apr 2014
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    ABSTRACT: An important development in digital X-ray imaging systems is a pulse amplitude measurement in each pixel in real-time. A single readout pixel usually has the dimensions of 100 µm × 100 µm or lower, and as it has to accommodate the analog front-end amplifier and digital back-end readout logic, the area available for an ADC is extremely low. Thus, in the design of the ADC the most emphasis has to be put on decreasing its silicon area. Also, as a single readout chip consists of thousands of pixels, the allowed power budget per pixel is in the order of tens of microwatts, hence the power consumption of the converter has to be kept very low as well. This paper describes a design and measurement results of two 4-bit flash ADC prototypes, fabricated in 180 nm and 40 nm processes, which fit into a single pixel and can be used in future X-ray imaging systems. To make the comparison more meaningful, both designs share exactly the same architecture, have identical resolution and sample rate. The architecture of the design, layout comparison and obtained test results are presented.
    No preview · Conference Paper · Apr 2014
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    ABSTRACT: The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected.
    No preview · Article · Jan 2014 · IEEE Transactions on Nuclear Science
  • A. Drozd · P. Maj
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    ABSTRACT: X-ray imaging is widely used in medicine in classic radiography, X-ray computed tomography and structural characterization of materials. X-ray detectors working in single photon counting mode, which register and process each photon separately, become more and more popular due to the possibility of imaging contrast enhancement. This paper presents problems of nonuniformity in imaging using this type of pixel X-ray detectors and methods of its correction.
    No preview · Article · Jan 2014 · Przeglad Elektrotechniczny
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    Full-text · Dataset · Dec 2013