Publications (19)13.89 Total impact
- [Show abstract] [Hide abstract] ABSTRACT: In addition to simulating lithography process effects, process models must accommodate pattern distortion due to the etching process. An etching bias modeling method and a staged correction strategy have been developed to compensate for such patterning process effects efficiently. However, the staged correction strategy may cause inaccurate compensation of patterning process effects since the patterns used to simulate etching process effects are assumed to be rectilinear. In fact, the patterns will be distorted during the lithography process. Therefore, a promising correction strategy that incorporates a recently developed optical proximity correction algorithm is proposed to deal with this problem. It can compensate for lithography and etching process effects simultaneously. In order to conduct this study, the etching bias modeling method is investigated by rigorous process simulations. The resulting model provides a reasonable fit to the measured data from the process simulations and can simulate etching process effects reasonably well. The performance of the proposed correction strategy in terms of correction accuracy and run time is examined. Numerical experiments show that the correction accuracy obtained is significantly improved compared with that obtained by the staged correction strategy. However, the total run time required is increased by a factor of ~2.5, which is practically acceptable for full-chip correction.
- [Show abstract] [Hide abstract] ABSTRACT: A method for compensating proximity effects of particle beam lithography processes is provided. The method includes the following steps. A control pattern is provided. A dissection process is provided. A set of control points are provided. The control pattern is defined as an input pattern of a lithography process. A target pattern is provided. A set of target points are produced. A set of target measurement values are provided. An actual pattern is defined. A set of actual measurement values are provided. A set of comparison values are calculated. An adjusting strategy is provided. A corrected pattern is produced. The corrected pattern is defined as an updated input of the lithography process.
- [Show abstract] [Hide abstract] ABSTRACT: Fast and robust metrologies for retrieving large amount of accurate wafer data is the key to meet the ever stricter semiconductor manufacturing process control such as critical dimension (CD) and overlay as the industry moving towards 22 nm or smaller designs. Scatterometry emerges due to its non-destructivity and rapid availability for accurate wafer data. In this paper we simulate the ability of a new scatterometry method to show its accurate control over lithography model and OPC model calibrations. The new method directly utilizes scattering signals of scatterometry to control the process instead of using numerically analyzed dimensional parameters such as CD and side wall angle (SWA). The control can be achieved by optimizing the scattering signal of one process by tuning numerical aperture (NA), sigma, or lens aberration to match the signal of the target process. In this work only sigma is used for optimization. We found that when the signals of both processes are matched with minimized optimization error, CD of the grating profiles on the wafers are also minimized. This result enables valid lithography process control and model calibration with the new method.
- [Show abstract] [Hide abstract] ABSTRACT: Electron-beam–direct-write lithography at lower accelerating voltages has been considered as a candidate for next-generation lithography. Although long-range proximity effects are substantially reduced with the voltage, proximity effect correction (PEC) is still necessary since short-range proximity effects are relatively prominent. The effectiveness of model-based PEC can be limited severely if an inaccurate point spread function (PSF) characterizing electron scattering within resist is adopted. Recently, a new PSF form using a promising calibration method has been developed to more accurately characterize the electron scattering and thus significantly improve patterning fidelity at 5 keV. However, influences of adopting the conventional and new PSF forms for the usage of patterning practical circuit layouts have not been intensively studied. This work extensively investigates impacts of PSF accuracy on patterning prediction and PEC under different resist thickness conditions suitable for various lithographic half-pitch nodes, where the critical features of practical circuit layouts are used to quantitatively evaluate their performance. In addition, patterning fidelity limitation suffered from proximity effects is examined to determine whether PEC should be applied. Simulation results indicate that the new PSF form can significantly improve the fitting accuracy, patterning prediction, and PEC results over the conventional PSF forms, especially for circuit layouts with smaller feature sizes.
- [Show abstract] [Hide abstract] ABSTRACT: Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.
- [Show abstract] [Hide abstract] ABSTRACT: Electron-beam lithography is one of the promising candidates to replace optical projection lithography due to its high resolution and maskless direct-write capability. In order to achieve the throughput requirement for high-volume manufacturing, miniaturized electro-optics elements are utilized to drive massively parallel beams simultaneously. In high-throughput multiple-electron-beam systems, beam positioning drift problems can become quite serious due to several factors such as thermal distortion and fabrication errors of electron optics. In single-beam systems, periodic recalibration with reference markers on the wafer can be utilized to achieve beam placement accuracy. This technique is not easy for multiple-beam systems. In this article, an innovative in situ two-dimensional electron-beam position monitoring system for multiple-electron-beam lithography is studied. An array of miniaturized electron detectors to measure scattered electrons from the substrate is placed above the wafer. It is assumed that the detector array signals are correlated with the distribution of electron trajectories, and the change of trajectory distortion due to the beam drift can be predicted by Monte Carlo electron-scattering simulation. A standard quadrant detection (SQD) method and a linear least-squares (LLS) method are used to estimate the beam drift from the detector array signals. Simulation results indicate that while the estimation uncertainty of both methods can be reduced substantially when the number of detected electrons is large enough. The LLS method always outperforms the SQD one regardless the detected electron numbers.
- [Show abstract] [Hide abstract] ABSTRACT: The conventional correction strategy used to compensate for imaging errors in extreme ultraviolet (EUV) lithography is accomplished by incorporating independent corrections in which rule-based corrections are used to compensate for EUV-specific imaging effects such as mask shadowing, and a model-based correction is used to compensate for proximity effects. Because most rule-based corrections are empirically developed by using simple Manhattan patterns, some of the simplified approximation approaches would not be applicable in a circuit layout with complicated geometric patterns. These kinds of approximation approaches can lead to ineffective corrections of EUV-specific imaging effects, resulting in inaccurate patterns printed on a wafer which will significantly alter the electrical characteristics of fabricated circuits. In order to prevent the problems due to rule-based corrections, a promising correction strategy has been proposed to simultaneously deal with EUV-specific imaging effects and proximity effects. In this study, the impact of two different correction strategies on the critical dimension (CD) variation caused by defocus and the deviation of electrical characteristics from the design intent is explored. Numerical experiments indicate that the variability of CD and electrical characteristics is significantly improved by the proposed correction strategy.
- [Show abstract] [Hide abstract] ABSTRACT: A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several regular mask geometries and practical design layouts.
- [Show abstract] [Hide abstract] ABSTRACT: Delta-chrome optical proximity correction (OPC) has been widely adopted in lithographic patterning for semiconductor manufacturing. During the delta-chrome OPC iteration, a predetermined amount of chrome is added or subtracted from the mask pattern. With this chrome change, the change of exposure intensity error (IE) or the change of edge placement error (EPE) between the printed contour and the target pattern is then calculated based on standard Kirchhoff approximation. Linear approximation is used to predict the amount of the proper chrome change to remove the correction error. This approximation can be very fast and effective, but must be performed iteratively to capture interactions between chrome changes. As integrated circuit (IC) design shrinks to the deep sub-wavelength regime, previously ignored nonlinear process effects, such as three-dimensional (3D) mask effects and resist development effects, become significant for accurate prediction and correction of proximity effects. These nonlinearities challenge the deltachrome OPC methodology. The model response to mask pattern perturbation by linear approximation can be readily computed but inaccurate. In fact, computation of the mask perturbation response becomes complex and expensive. A non-delta-chrome OPC methodology with IE-based feedback compensation is proposed. It determines the amount of the proper chrome change based on IE without intensive computation of mask perturbation response. Its effectiveness in improving patterning fidelity and runtime is examined on a 50-nm practical circuit layout. Despite the presence and the absence of nonlinear 3D mask effects, our results show the proposed non-delta-chrome OPC outperforms the deltachrome one in terms of patterning fidelity and runtime. The results also demonstrate that process models with 3D mask effects limit the use of delta-chrome OPC methodology.
- [Show abstract] [Hide abstract] ABSTRACT: The Finite-Difference Time-Domain (FDTD) method is used to study the scattering effects of extreme ultraviolet (EUV) mask. It requires significant amounts of memory and computation time as the fine grid size is needed for simulation. Theoretically, the accuracy can be increased as the mesh size is decreased in FDTD simulation. However, it is not easy to get the accurate simulation results for the multilayer (ML) structures by FDTD method. The transmission line theory is used to calculate the equivalent refractive index for EUV mask ML to simulate the ML as one layer of bulk artificial material. The reflectivities for EUV light with the normal incidence and small-angle oblique incidence in the bulk artificial material and EUV mask ML are simulated by FDTD method. The Fresnel's equation is used to evaluate the numerical errors for these FDTD simulations, and the results show good agreement between them. Using the equivalent refractive index material for EUV multilayer mask can reduce the computation time and have the accuracy with tolerable numerical errors. The ML structure with periodic surface roughness is also studied by this method, and it shows that only half of computation time is needed to substitute ML to a bulk equivalent refractive index material in FDTD simulations. This proposed method can accelerate the simulations of EUV mask designs.
- [Show abstract] [Hide abstract] ABSTRACT: Extreme ultraviolet (EUV) lithography is one of the promising candidates for device manufacturing with features smaller than 22 nm. Unlike traditional optical projection systems, EUV light needs to rely on reflective optics and masks with an oblique incidence for image formation in photoresist. The consequence of using a reflective projection system can result in horizontal-vertical (H-V) bias and pattern shift, which are generally referred as shadowing. Approaches proposed to compensate for shadowing effect include changing mask topography, modifying mask focus, and biasing features along the azimuth angle, which are all rule-based. However, the complicated electromagnetic interaction between closely placed circuit patterns can not only induce additional optical proximity effect but also change the shadowing effect. These detailed phenomena cannot be completely taken into account by the rule-based approaches. A fully model-based approach, which integrates an in-house model-based optical proximity correction (OPC) algorithm with rigorous three-dimensional (3D) EUV mask simulation, is proposed to simultaneously compensate for shadowing and optical proximity effects with better pattern transfer fidelity and process windows. Preliminary results indicate that this fully model-based approach outperforms rule-based ones, in terms of geometric printability under process variations.
- [Show abstract] [Hide abstract] ABSTRACT: Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design. In this paper, TCAD device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors. It is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region. A new EGL extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity. Preliminary results verified by TCAD simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved. The method is readily applicable to calibration with real silicon data.
- [Show abstract] [Hide abstract] ABSTRACT: Accelerating voltage as low as 5 kV for operation of the electron-beam micro-columns as well as solving the throughput problem is being considered for high-throughput direct-write lithography for the 22-nm half-pitch node and beyond. The development of efficient proximity effect correction (PEC) techniques at low-voltage is essential to the overall technology. For realization of this approach, a thorough understanding of electron scattering in solids, as well as precise data for fitting energy intensity distribution in the resist are needed. Although electron scattering has been intensively studied, we found that the conventional gradient based curve-fitting algorithms, merit functions, and performance index (PI) of the quality of the fit were not a well posed procedure from simulation results. Therefore, we proposed a new fitting procedure adopting a direct search fitting algorithm with a novel merit function. This procedure can effectively mitigate the difficulty of conventional gradient based curve-fitting algorithm. It is less sensitive to the choice of the trial parameters. It also avoids numerical problems and reduces fitting errors. We also proposed a new PI to better describe the quality of the fit than the conventional chi-square PI. An interesting result from applying the proposed procedure showed that the expression of absorbed electron energy density in 5keV cannot be well represented by conventional multi-Gaussian models. Preliminary simulation shows that a combination of a single Gaussian and double exponential functions can better represent low-voltage electron scattering.
- [Show abstract] [Hide abstract] ABSTRACT: Model-based Optical Proximity Correction (MBOPC) has become one of the most important resolution enhancement technologies (RETs), which can effectively improve the image fidelity and process robustness. MBOPC is performed by iteratively shifting the polygon edges of mask patterns until convergence requirements are achieved. In this paper, we specifically discuss the design of feedback controllers to improve MBOPC convergence. Effective controller design rules are derived from the OPC results of several circuit layouts. Meanwhile, resist models also significantly affect MBOPC convergence. Two kinds of resist model have been proposed for MBOPC such as constant threshold resist model (CTRM) and variable threshold resist model (VTRM). We propose a novel CTRM, called pattern-based optimal threshold determination (PBOTD). By normalized mean square error (NMSE) formulation, appropriate threshold values with minimum NMSE can be determined to improve image fidelity, and effectively decrease iterations required. The effectiveness of applying both optimized controller and PBOTD is demonstrated on a 90-nm SRAM cell.
- [Show abstract] [Hide abstract] ABSTRACT: Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength regime. The poly gate distortion affects device electrical characteristics, including drive current (Ion), leakage current (Ioff), and threshold voltage (Vt). For circuits sensitive to layout, such as compact memory cells, electrical performances can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different ways.
National Taiwan University
T’ai-pei, Taipei, Taiwan
- Department of Electrical Engineering