- [Show abstract] [Hide abstract] ABSTRACT: A wideband single-ended input and differential output low noise amplifier (LNA) employing the common-gate (CG) common-source (CS) structure is presented. The output of the CS transistor is utilized to boost the effective transconductance of the CG stage. The gain balance won’t be affected by the g m-boosting stage, because its gain is constant, and independent of process, voltage, and temperature. The composite CS stage, consisting of two parts, is first proposed to cancel the gain imbalance induced by the back-gate effect. The first part of the CS transistors employs the body-coupling technique, and the other part are the conventional CS transistors. For a proof-of-concept, the proposed balun-LNA is fabricated in a 0.13 μm CMOS process. The frequency band of the circuit is 0.5–3.7 GHz. The measured in-band average and maximum gain imbalance are 0.34, 0.7 dB, respectively. The phase imbalance range is −1° to 5°. A noise figure of 3.7–6.2 dB, and a minimum IIP3 of −7.1 dBm are obtained. Good input/output matching are achieved through the frequency band. The LNA consumes a power of 10.2 mW from a 1.5 V supply.
- [Show abstract] [Hide abstract] ABSTRACT: Nowadays digital radio systems are replacing analog radio systems. In this paper, a CMOS RF receiver with frequency synthesizer and analog baseband is introduced, which was fabricated with a 0.18-µm CMOS process for DRM/DAB wideband applications. In the system, a fully differential low noise amplifier with a noise cancelling technology is adopted It has achieved a gain of 11.69 dB. A harmonic rejection mixer was implemented to realize the rejections of 3rd- and 5th-order harmonics. As the local oscillator, a wide-band frequency synthesizer provides a phase noise of −125 dBc/Hz at 1-MHz offset. The designed RF receiver has achieved a conversion gain of 90 dB. The IIP3 of the receiver is in the range of −25 to −12 dBm, and the noise figure of 5.44-14.72 dB. The core circuits draw a current of 78.35 mA from a 1.8-V power supply and the chip occupies 6.46-mm2 die area.
- [Show abstract] [Hide abstract] ABSTRACT: This paper presents a 37 Gb/s phase locked-loop (PLL)-type clock recovery (CR) circuit designed and fabricated in 0.2-µm GaAs PHEMT process. The resonator of the modified LC-VCO is based on a compact circuit topology with high Q-value and better isolation. The active amplifier of the VCO is optimized with a combination of several circuit techniques to reduce phase noise and increase the operation speed. Resonant filters containing high-quality CPWs are employed in the signal preprocessor to accommodate the 37 Gb/s data rate. The measured figure of merit of the modified VCO is about −196 dBc/Hz at 37-GHz when the PLL is locked. The experimental results also demonstrate that the recovered clock signal of the CR circuit has a phase noise of −81.66 dBc/Hz at 50 kHz off the center frequency.
- [Show abstract] [Hide abstract] ABSTRACT: A novel low-IF double balanced CMOS Gilbert mixer with high linearity and conversion gain is presented in this paper. An innovative easy-implemented cross-coupled full differential multiple gated transistor topology is proposed to improve the linearity while maintaining the high conversion gain. In addition, a topology, which artfully combines the current-bleeding technology and the noise-cancelling technology, is introduced to reduce the noise figure. The prototype of the proposed circuit was fabricated in SMIC 0.18 μm CMOS process with a chip area of 0.32 × 0.24 mm2. The measurement results have exhibited an IIP3 of 10.2 dBm and a conversion gain of 17.8 dB with a power dissipation of 3.6 mW from 1.8 V supply. Compared to recently published studies, the proposed work has achieved a higher FoM.
- [Show abstract] [Hide abstract] ABSTRACT: The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. The proof-of-concept prototypes are designed in a 0.18-\(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The measurement results validate the analysis and simulation results well.
- [Show abstract] [Hide abstract] ABSTRACT: A novel topology of Q (quality factor)-enhanced dynamically self-biasing Class-C VCO is proposed in this article. It introduces a bridging capacitor to enhance the quality factor of the oscillator. The enhancement of the quality factor suppresses the squegging phenomenon and the harmonic distortion, and thus improves the phase noise and oscillation stability. The prototype of the proposed circuit was fabricated in SMIC 0.18 µm CMOS process and the measurement results showed a low phase noise of −125 dBc/Hz@1 MHz from 3.331 GHz carrier with a total power consumption of 3.36 mW from a 1.2 V supply. The proposed work exhibited an excellent Figure of Merit (FoM) of −190 dBc/Hz.
- [Show abstract] [Hide abstract] ABSTRACT: A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of −80 dBc/Hz at 10 kHz offset, −95 dBc/Hz at 100 kHz offset, and −120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.
Conference Paper: Design of a CMOS LC-VCO with low phase noise for UHF RFID reader
- [Show abstract] [Hide abstract] ABSTRACT: A novel crystal oscillator circuit with differential quadrature outputs is presented in this paper. It couples two differential Pierce structures with an annular cascade structure to realize differential quadrature outputs directly. A prototype of the circuit was fabricated in SMIC 0.18 μm CMOS process technology. The measurement results show that the maximum quadrature phase mismatch of adjoining signals is lower than 1.3° and the maximum amplitude mismatch is less than 1 %. Compared to the conventional quadrature signal implementations such as poly phase filter network, or a current mode logic divider, our proposed circuit can directly achieve differential quadrature outputs with much better phase noise and excellent differential quadrature matching. It proves potential application prospect in many radio frequency transceiver systems which require rigorous matching characteristics of differential quadrature local oscillator for excellent performance of image rejection.
- [Show abstract] [Hide abstract] ABSTRACT: In this presentation the motor function rebuilding of paralyzed limbs of the paraplegic patients caused by spinal cord injury and the hemiplegic patients after stroke and SCI is concerned. The biomedical methods and the traditional physical methods for the rehabilitation of two kinds of paralyses are reviewed. The core part is to discuss the neural and muscular signal regeneration and the limb function rebuilding based on the principles of communication and functional electrical stimulation - a novel concept developed by the speakers. For the communication, a microwave transmission system is incorporated. The construction of the whole bio-electronic system, the animal experiments, and the elementary experiments on healthy and paralyzed patients will be demonstrated.
Conference Paper: A low power variable gain amplifier with 50-dB dynamic range[Show abstract] [Hide abstract] ABSTRACT: This paper presents a new structure of variable gain amplifier (VGA) in which a modified Gilbert Cell is firstly proposed to implement a low power wide dynamic range VGA. The proposed VGA can provide 50-dB dynamic range within a linear error of 1-dB. Furthermore, the proposed circuit consumes less than 0.5-mA current and occupies about only 0.12-mm2 chip area, both of which are relatively low in terms of the wide dynamic range provided by it.
- [Show abstract] [Hide abstract] ABSTRACT: This paper presents a novel programmable assert threshold loss-of-signal (LOS) detector with fixed optical hysteresis for intelligent limiting amplifier (LA) using 0.5-μm 2P2M CMOS technology. By adjusting the gain of the LA, a programmable threshold range of 2–20 mVpp is implemented. The proposed detector circuit obtains a signal strength indication voltage V SIG and a reference voltage V REF, both of which can be dependent each other. With other special circuit design techniques, the detector circuit achieves stable LOS range, LOS hysteresis and LOS precision, and all of them are completely independent on all process, voltage supply and temperature deviations. This LOS detector is integrated with a 155-Mbps LA operating at a compatible supply voltage of 3.3 and 5.0 V. The measurement results demonstrate that the LOS detector achieves a stable programmable assert threshold and a 2 dB fixed optical hysteresis for a 155 Mbps input pseudo random sequence.
- [Show abstract] [Hide abstract] ABSTRACT: This article propose a novel tunable active inductor for high gain-bandwidth LNA. Using this active inductor, a noise-cancelling LNA with gain-peak technique is designed for DRM/DAB receiver. Consequently, a broader -3dB bandwidth is substantially achieved from the LNA. By adding a regulated capacitance and a feedback resistance into a conventional active inductor, the quality-factor and the inductance can be increased. The tuning range is widened and the performances of the active inductor are insensitive for the PVT variations at the same time. The proposed circuit is verified with a 0.18-μm CMOS process, the post-simulation results demonstrate that the LNA has broader 3-dB bandwidth.
- [Show abstract] [Hide abstract] ABSTRACT: An integrated power distributed amplifier, fabricated in a low-cost 2-μm GaAs heterojunction bipolar transistor (HBT) technology, is implemented in this letter. A tapered collector line structure combined with the input capacitive coupling technique is used to improve the bandwidth and power efficiency simultaneously. The measurement results give a gain of 8.1dB with a gain flatness of ±0.5dB over a frequency range from 1 to 12 GHz. The output 1-dB compressing point is 13.9 dBm at 5 GHz and the associated power-added efficiency is 21.9%. Our work presents very good figure of merit among the recently published distribution amplifiers with different technologies. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26126
- [Show abstract] [Hide abstract] ABSTRACT: The characteristic impedance of L-type and T-type networks are investigated for the distributed amplifier (DA) design respectively. The analysis shows that the L-type network has better frequency characteristics than the T-type one. Two distributed amplifiers with L- and T-type network are designed with 2-μm GaAs HBT process for comparison. The simulation results demonstrate that the DA with L-type network has broader 3-dB bandwidth than that of the DA with T-type network.
- [Show abstract] [Hide abstract] ABSTRACT: A 50MHz-1GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) is presented in this article. The circuit was designed with 0.15um InGaAs PHEMT process. The ADS simulation results showed it gave excellent Noise Figure of 1.36dB and high linearity up to 17dBm IIP3 with 75Ohm systems. It is especially suitable in the applications such as cellular telephone base station driver amplifiers. the Cable TV etc.