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Publications (6)0 Total impact

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    ABSTRACT: This paper discusses integration issues related to CVD WSi<sub>x </sub> polycide process for 170-nm DRAM technology. Some problems encountered were: etch pits, sidewall protrusions, and electrical gate oxide thickness variations. The etch pits were eliminated by hardware and process modifications, to achieve a uniform W concentration in the as-deposited WSi<sub>x</sub> film. Sidewall protrusions were eliminated by incorporating an RTA anneal prior to sidewall oxidation of the polycide stack. The variations in electrical gate oxide thickness are associated with high fluorine levels, and these were controlled by using a calibrated MFC for WF6 gas during the CVD WSi<sub>x</sub> deposition
    No preview · Conference Paper · Feb 2000
  • Y. Karzhavin
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    ABSTRACT: Semiconductor manufacturing facility White Oak Semiconductor is working toward the implementation of a challenging goal: significant increase of wafer starts per week without adding new floor space to the existing clean room area. To this end a Productivity Improvement Project has been deployed across the factory. The Project is concentrated on efforts to improve equipment productivity, optimize equipment utilization, and the effectiveness of personnel. One of the most challenging areas of the factory is Etch. This paper focuses on the productivity improvement activities in the Etch area
    No preview · Conference Paper · Feb 2000
  • Y. Karzhavin
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    ABSTRACT: This paper presents results of the STI etch process developed for 64 MB Trench Capacitor DRAM technology, scalable for future generations of the product as well. An aspect ratio of 2.5 was achieved. High uniformity of the trench depths and after etch Critical Dimensions (ACI CD) are demonstrated. A low etch bias <0.01 μm was achieved. This manufacturable STI process for sub-0.2 μm technologies was developed for applications in an MRlE etcher with an electrostatic chuck (ESC) and Silicon shadow ring. The Si-ring provided 60-100% improvement in the STI depth and ACI CD stability across the wafer. Mean time between chamber cleans and cost of the process kit consumable parts improved 30 - 50%
    No preview · Conference Paper · Feb 1999
  • Y. Karzhavin · W. Wu
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    ABSTRACT: Plasma induced charging has been identified as a cause for uncontrolled pattern-dependent etch rate modification and physical damage of the etching pattern. Undercutting (notching) of metal lines and underlayer-dependent oxide etch have been studied using a noncontact oxide charging monitor technique. It is shown that the dry etching process is strongly affected by plasma induced wafer charging and by underlying conducting films. The undercutting of metal lines occurs when the metal pattern is electrically connected to the substrate. Specially designed oxide monitor wafers with an metal pattern underlayer were used for charging distribution studies. It was demonstrated that the connection of a metal underlayer to the silicon substrate causes strong accumulation of positive charges in the wafer center. Strong metal line undercutting occurred under these conditions. The resulting pattern of plasma induced charge correlates to the undercutting pattern
    No preview · Conference Paper · Oct 1998
  • Y. Karzhavin · W. Wu
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    ABSTRACT: Plasma induced charging has been identified as a cause of uncontrolled pattern-dependent etch rate modification and physical etching pattern damage. It is demonstrated that plasma nonuniformity and the pattern distribution of conducting layers under the wafer surface play an important role in the final charging distribution, resulting in physical damage, device damage and etch process failure. Undercut or notching of metal lines and underlayer-dependent oxide etch are studied using a noncontact oxide charging monitor technique. It is shown that the dry etch process is strongly affected by plasma induced wafer charging. Undercutting of metal lines occurs when the metal pattern has an electrical connection to the substrate. Oxide charging monitor wafers with a metal underlayer connected to the silicon substrate have charging redistribution with a strong accumulation of positive charge in the wafer center. The induced charge pattern is correlated to the undercut pattern
    No preview · Conference Paper · Jul 1998
  • Y. Karzhavin · W. Wu
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    ABSTRACT: Plasma induced charging damage and oxide degradation after metal and poly etch and photo-resist strip were studied using unpatterned oxide wafer technique. The time dependence of plasma induced charging, internal oxide damage and charging “fingerprint” were investigated for poly etch, metal etch and photo-resist strip after metal etch processes. Comparison of oxide charging monitor results and SPIDER antennae structures data for photo-resist strip process is presented
    No preview · Conference Paper · Oct 1997